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path: root/target/m68k/translate.c
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* target/m68k: use insn_pc to generate instruction fault addressLaurent Vivier2018-01-041-20/+20
* target/m68k: fix gen_get_ccr()Laurent Vivier2018-01-041-1/+0Star
* target-m68k: sync CC_OP before gen_jmp_tb()Laurent Vivier2018-01-041-1/+2
* target/m68k: fix set_cc_op()Laurent Vivier2017-12-211-0/+1
* target/m68k: remove unused variable gen_throws_exceptionLaurent Vivier2017-12-211-10/+0Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-5/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-2/+10
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
* | tcg: Remove TCGV_EQUAL*Richard Henderson2017-10-241-1/+1
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* target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-1/+6
* m68k/translate: fix incorrect copy/pastePhilippe Mathieu-Daudé2017-07-311-1/+1
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé2017-07-191-2/+1Star
* target/m68k: add fmovemLaurent Vivier2017-06-291-30/+63
* target/m68k: add explicit single and double precision operations (part 2)Laurent Vivier2017-06-291-4/+22
* target/m68k: add fsglmul and fsgldivLaurent Vivier2017-06-291-0/+6
* target/m68k: add explicit single and double precision operationsLaurent Vivier2017-06-291-5/+35
* target/m68k: add fmovecrLaurent Vivier2017-06-291-1/+12
* target/m68k: add fscc.Laurent Vivier2017-06-291-79/+131
* target-m68k: add FPCR and FPSRLaurent Vivier2017-06-211-91/+260
* target-m68k: use floatx80 internallyLaurent Vivier2017-06-211-227/+419
* target-m68k: move fmove CR to a functionLaurent Vivier2017-06-211-25/+31
* target-m68k: define ext_opsizeLaurent Vivier2017-06-151-19/+24
* target/m68k: fix V flag for CC_OP_SUBxLaurent Vivier2017-06-151-1/+1
* target/m68k: implement rtdLaurent Vivier2017-06-071-0/+11
* target-m68k: increment/decrement with SPLaurent Vivier2017-01-141-2/+12
* target-m68k: CAS doesn't need aligned accessLaurent Vivier2017-01-141-1/+0Star
* target-m68k: manage pre-dec et post-inc in CASLaurent Vivier2017-01-141-0/+9
* target-m68k: fix gen_flush_flags()Laurent Vivier2017-01-141-1/+2
* target-m68k: fix bit operation with immediate valueLaurent Vivier2017-01-141-3/+10
* target-m68k: Implement bfffoRichard Henderson2017-01-141-1/+38
* target-m68k: Implement bitfield ops for memoryRichard Henderson2017-01-141-2/+140
* target-m68k: Implement bitfield ops for registersRichard Henderson2017-01-141-0/+210
* target-m68k: free TCG variables that are notLaurent Vivier2016-12-271-9/+32
* target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier2016-12-271-0/+391
* target-m68k: Inline shiftsRichard Henderson2016-12-271-25/+201
* target-m68k: Do not cpu_abort on undefined insnsRichard Henderson2016-12-271-3/+5
* target-m68k: Implement 680x0 movemLaurent Vivier2016-12-271-23/+107
* target-m68k: add cas/cas2 opsLaurent Vivier2016-12-271-0/+154
* target-m68k: add abcd/sbcd/nbcdLaurent Vivier2016-12-271-0/+220
* target-m68k: add 680x0 divu/divs variantsLaurent Vivier2016-12-271-37/+47
* target-m68k: add 64bit mullLaurent Vivier2016-12-271-12/+50
* target-m68k: add cmpmLaurent Vivier2016-12-271-0/+16
* target-m68k: Split gen_lea and gen_eaRichard Henderson2016-12-271-53/+59
* target-m68k: Delay autoinc writebackRichard Henderson2016-12-271-20/+64
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+3595
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