summaryrefslogtreecommitdiffstats
path: root/target/mips/cp0_helper.c
Commit message (Collapse)AuthorAgeFilesLines
* target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolderPhilippe Mathieu-Daudé2021-05-021-1706/+0Star
| | | | | | | | | | | Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-20-f4bug@amsat.org>
* target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé2021-01-141-9/+9
| | | | | | | | | | | The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-131-1/+1
| | | | | | | | | | Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
* target/mips: Remove unused headers from cp0_helper.cPhilippe Mathieu-Daudé2020-12-131-3/+1Star
| | | | | | | | | Remove unused headers and add missing "qemu/log.h" since qemu_log() is called. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-5-f4bug@amsat.org>
* target/mips: Do not include CP0 helpers in user-mode emulationPhilippe Mathieu-Daudé2020-12-131-4/+0Star
| | | | | | | | | | | CP0 helpers are restricted to system-mode emulation. Do not intent do build cp0_helper.c in user-mode (this allows to simplify some #ifdef'ry). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201109090422.2445166-3-f4bug@amsat.org>
* target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MINPhilippe Mathieu-Daudé2020-12-131-2/+3
| | | | | | | | | | | | Replace magic values related to page size: 12 -> TARGET_PAGE_BITS_MIN 13 -> CP0PM_MASK Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201109090422.2445166-2-f4bug@amsat.org>
* target/mips: Fix PageMask with variable page sizeJiaxun Yang2020-11-091-6/+21
| | | | | | | | | | | | | | Our current code assumed the target page size is always 4k when handling PageMask and VPN2, however, variable page size was just added to mips target and that's no longer true. Fixes: ee3863b9d414 ("target/mips: Support variable page size") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1604636510-8347-2-git-send-email-chenhc@lemote.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Replaced find_first_zero_bit() by cto32()] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Fix Lesser GPL version numberChetan Pant2020-11-031-1/+1
| | | | | | | | | | | | | There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201016143509.26692-1-chetan4windows@gmail.com> [PMD: Split hw/ vs target/] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé2020-10-171-0/+25
| | | | | | | | | | | | | The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register used as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>
* target/mips: Remove identical if/else branchesAleksandar Markovic2020-07-141-8/+1Star
| | | | | | | | | | | | | | | | | | Remove the segment: if (other_tc == other->current_tc) { tccause = other->CP0_Cause; } else { tccause = other->CP0_Cause; } Original contributor can't remember what was his intention. Fixes: 5a25ce9487 ("mips: Hook in more reg accesses via mttr/mftr") Buglink: https://bugs.launchpad.net/qemu/+bug/1885718 Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200701182559.28841-2-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/mips: Separate CP0-related helpers into their own fileAleksandar Markovic2020-02-041-0/+1678
For clarity and easier maintenence, create target/mips/cp0_helper.c, and move all CP0-related content form target/mips/op_helper.c to that file. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Message-Id: <1580745443-24650-2-git-send-email-aleksandar.markovic@rt-rk.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-04 02:01:07 +0100