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path: root/target/mips/internal.h
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* target/mips: Optimize regnames[] arraysPhilippe Mathieu-Daudé2021-06-241-1/+1
* target/mips: Move TCG source files under tcg/ sub directoryPhilippe Mathieu-Daudé2021-05-021-11/+0Star
* target/mips: Move CP0 helpers to sysemu/cp0.cPhilippe Mathieu-Daudé2021-05-021-4/+5
* target/mips: Move exception management code to exception.cPhilippe Mathieu-Daudé2021-05-021-13/+0Star
* target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.cPhilippe Mathieu-Daudé2021-05-021-7/+0Star
* target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scopePhilippe Mathieu-Daudé2021-05-021-6/+0Star
* target/mips: Move tlb_helper.c to tcg/sysemu/Philippe Mathieu-Daudé2021-05-021-5/+0Star
* target/mips: Restrict mmu_init() to TCGPhilippe Mathieu-Daudé2021-05-021-3/+0Star
* target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCGPhilippe Mathieu-Daudé2021-05-021-4/+0Star
* target/mips: Move physical addressing code to sysemu/physaddr.cPhilippe Mathieu-Daudé2021-05-021-1/+24
* target/mips: Move cpu_signal_handler definition aroundPhilippe Mathieu-Daudé2021-05-021-5/+4Star
* target/mips: Introduce tcg-internal.h for TCG specific declarationsPhilippe Mathieu-Daudé2021-05-021-4/+3Star
* target/mips: Merge do_translate_address into cpu_mips_translate_addressPhilippe Mathieu-Daudé2021-05-021-1/+1
* target/mips: Declare mips_env_set_pc() inlined in "internal.h"Philippe Mathieu-Daudé2021-05-021-0/+10
* target/mips: Restrict mips_cpu_dump_state() to cpu.cPhilippe Mathieu-Daudé2021-05-021-1/+0Star
* target/mips: Optimize CPU/FPU regnames[] arraysPhilippe Mathieu-Daudé2021-05-021-2/+2
* target/mips: Make CPU/FPU regnames[] arrays globalPhilippe Mathieu-Daudé2021-05-021-0/+3
* target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2021-02-211-4/+4
* target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2021-02-211-1/+1
* target/mips: Remove access_type argument from map_address() handlerPhilippe Mathieu-Daudé2021-02-211-4/+4
* target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé2021-01-141-0/+2
* target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSAPhilippe Mathieu-Daudé2021-01-141-1/+1
* target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé2021-01-141-0/+1
* target/mips: Move common helpers from helper.c to cpu.cPhilippe Mathieu-Daudé2021-01-141-0/+2
* target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé2021-01-141-49/+0Star
* target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé2021-01-141-2/+2
* target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips: Use FloatRoundMode enum for FCR31 modes conversionPhilippe Mathieu-Daudé2020-12-131-1/+2
* target/mips: Move cpu definitions, reset() and realize() to cpu.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
* target/mips: Explicit Release 6 MMU typesPhilippe Mathieu-Daudé2020-12-131-4/+5
* target/mips: Include "exec/memattrs.h" in 'internal.h'Philippe Mathieu-Daudé2020-12-131-0/+1
* target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé2020-10-171-1/+1
* target/mips: Fix some comment spelling errorszhaolichang2020-10-171-1/+1
* target/mips: Add Loongson-3 CPU definitionHuacai Chen2020-06-091-0/+2
* target/mips: fpu: Refactor conversion from ieee to mips exception flagsAleksandar Markovic2020-06-091-1/+0Star
* gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
* target/mips: Add implementation of GINVT instructionYongbok Kim2020-01-291-0/+1
* target/mips: Clean up internal.hAleksandar Markovic2019-10-011-23/+37
* target/mips: Switch to do_transaction_failed() hookPeter Maydell2019-09-121-3/+5
* target/mips: rationalise softfloat includesAlex Bennée2019-08-191-0/+7
* migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster2019-08-161-1/+1
* target/mips: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1Star
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+1
* target/mips: Implement hardware page table walker for MIPS32Yongbok Kim2018-10-181-0/+1
* target/mips: Improve DSP R2/R3-related namingStefan Markovic2018-10-181-11/+19
* target/mips: Add availability control for DSP R3 ASEStefan Markovic2018-10-181-3/+8
* target/mips: Increase 'supported ISAs/ASEs' flag holder sizePhilippe Mathieu-Daudé2018-10-181-1/+1
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