| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | mips: introduce internal.h and cleanup cpu.h | Philippe Mathieu-Daudé | 2017-09-21 | 1 | -0/+1 |
| * | target-mips: apply CP0.PageMask before writing into TLB entry | Leon Alrae | 2017-08-02 | 1 | -2/+3 |
| * | target/mips: Add segmentation control registers | James Hogan | 2017-07-20 | 1 | -0/+24 |
| * | target/mips: Add an MMU mode for ERL | James Hogan | 2017-07-20 | 1 | -0/+10 |
| * | target/mips: Abstract mmu_idx from hflags | James Hogan | 2017-07-20 | 1 | -2/+2 |
| * | target/mips: Add CP0_Ebase.WG (write gate) support | James Hogan | 2017-07-20 | 1 | -2/+10 |
| * | target/mips: Weaken TLB flush on UX,SX,KX,ASID changes | James Hogan | 2017-07-20 | 1 | -1/+1 |
| * | target/mips: Fix TLBWI shadow flush for EHINV,XI,RI | James Hogan | 2017-07-20 | 1 | -2/+10 |
| * | target/mips: hold BQL for timer interrupts | Yongbok Kim | 2017-03-09 | 1 | -3/+18 |
| * | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 2017-01-13 | 1 | -4/+4 |
| * | target-mips: Use clz opcode | Richard Henderson | 2017-01-10 | 1 | -22/+0 |
| * | Move target-* CPU file into a target/ folder | Thomas Huth | 2016-12-20 | 1 | -0/+4196 |
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index : bwlp/qemu.git | |
| Experimental fork of QEMU with video encoding patches | OpenSLX |
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