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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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mips
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tcg
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msa.decode
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/mips: Remove one MSA unnecessary decodetree overlap group
Philippe Mathieu-Daudé
2021-11-02
1
-182
/
+180
*
target/mips: Remove generic MSA opcode
Philippe Mathieu-Daudé
2021-11-02
1
-2
/
+0
*
target/mips: Convert CTCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+4
*
target/mips: Convert CFCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+4
*
target/mips: Convert MSA MOVE.V opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+6
*
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+2
*
target/mips: Convert MSA COPY_U opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+1
*
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+8
*
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+53
*
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+3
*
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+11
*
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+6
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+39
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+9
*
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+8
*
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+3
*
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+2
*
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+20
*
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+4
*
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+8
*
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+3
*
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+19
*
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-0
/
+16
*
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+7
*
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2021-11-02
1
-8
/
+7
*
target/mips: Rename 'rtype' as 'r'
Philippe Mathieu-Daudé
2021-08-25
1
-2
/
+2
*
target/mips: Merge msa32/msa64 decodetree definitions
Philippe Mathieu-Daudé
2021-06-24
1
-0
/
+31
