bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	mips: split cpu_mips_realize_env() out of cpu_mips_init()	Philippe Mathieu-Daudé	2017-09-21	1	-7/+12
*	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé	2017-09-21	1	-0/+1
*	target/mips: Fix RDHWR CC with icount	James Hogan	2017-08-02	1	-0/+11
*	target/mips: Drop redundant gen_io_start/stop()	James Hogan	2017-08-02	1	-8/+0
*	target/mips: Use BS_EXCP where interrupts are expected	James Hogan	2017-08-02	1	-13/+34
*	mips: Add KVM T&E segment support for TCG	James Hogan	2017-08-02	1	-2/+2
*	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	James Hogan	2017-08-02	1	-4/+0
*	target/mips: Add segmentation control registers	James Hogan	2017-07-20	1	-0/+88
*	target/mips: Abstract mmu_idx from hflags	James Hogan	2017-07-20	1	-1/+1
*	target/mips: Decode microMIPS EVA load & store instructions	James Hogan	2017-07-20	1	-4/+115
*	target/mips: Decode MIPS32 EVA load & store instructions	James Hogan	2017-07-20	1	-0/+106
*	target/mips: Prepare loads/stores for EVA	James Hogan	2017-07-20	1	-35/+42
*	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	2017-07-20	1	-3/+5
*	target/mips: Fix MIPS64 MFC0 UserLocal on BE host	James Hogan	2017-07-20	1	-2/+3
*	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	2017-07-19	1	-3/+2
*	target/mips: optimize WSBH, DSBH and DSHD	Aurelien Jarno	2017-07-17	1	-6/+12
*	target/mips: fix msa copy_[s\|u]_df rd = 0 corner case	Miodrag Dinic	2017-07-11	1	-2/+6
*	target/mips: optimize indirect branches	Aurelien Jarno	2017-06-05	1	-1/+1
*	target/mips: optimize cross-page direct jumps in softmmu	Aurelien Jarno	2017-06-05	1	-1/+1
*	target/mips: fix delay slot detection in gen_msa_branch()	Yongbok Kim	2017-03-20	1	-1/+1
*	target-mips: replace few LOG_DISAS() with trace points	Philippe Mathieu-Daudé	2017-03-20	1	-14/+11
*	target-mips: replace break by goto cp0_unimplemented	Philippe Mathieu-Daudé	2017-03-20	1	-44/+44
*	target-mips: log bad coprocessor0 register accesses with LOG_UNIMP	Philippe Mathieu-Daudé	2017-03-20	1	-6/+6
*	target-mips: remove old & unuseful comments	Philippe Mathieu-Daudé	2017-03-20	1	-4/+0
*	target-mips: Provide function to test if a CPU supports an ISA	Paul Burton	2017-02-21	1	-0/+10
*	target-mips: Use clz opcode	Richard Henderson	2017-01-10	1	-7/+16
*	target-mips: Use the new extract op	Richard Henderson	2017-01-10	1	-7/+5
*	Move target-* CPU file into a target/ folder	Thomas Huth	2016-12-20	1	-0/+20423