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path: root/target/mips/translate.c
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* target/mips: fetch code with translator_ldPhilippe Mathieu-Daudé2021-02-211-10/+10
* target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-2/+0Star
* target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-2/+0Star
* target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-4/+1Star
* target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-4/+0Star
* target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-4/+1Star
* target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2021-01-141-2/+0Star
* target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2021-01-141-1/+0Star
* target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé2021-01-141-2/+0Star
* target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé2021-01-141-23/+5Star
* target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé2021-01-141-0/+5
* target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé2021-01-141-32/+4Star
* target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé2021-01-141-22/+10Star
* target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé2021-01-141-2249/+0Star
* target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2021-01-141-2/+2
* target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé2021-01-141-21/+48
* target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé2021-01-141-29/+28Star
* target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2021-01-141-13/+18
* target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé2021-01-141-5/+9
* target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé2021-01-141-12/+11Star
* target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-141-4/+2Star
* target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé2021-01-141-5/+3Star
* target/mips/translate: Extract decode_opc_legacy() from decode_opc()Philippe Mathieu-Daudé2021-01-141-20/+29
* target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2021-01-141-70/+0Star
* target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2021-01-141-12/+12
* target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2021-01-141-362/+367
* target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé2021-01-141-3/+3
* target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2021-01-141-38/+14Star
* target/mips/translate: Extract DisasContext structurePhilippe Mathieu-Daudé2021-01-141-37/+1Star
* target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé2021-01-141-0/+1
* target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé2021-01-141-213/+213
* target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé2021-01-141-69/+69
* target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé2021-01-141-27/+27
* target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé2021-01-141-2/+2
* target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1Philippe Mathieu-Daudé2021-01-141-5/+5
* target/mips: Move cpu definitions, reset() and realize() to cpu.cPhilippe Mathieu-Daudé2020-12-131-240/+0Star
* target/mips: Extract cpu_supports*/cpu_set* translate.cPhilippe Mathieu-Daudé2020-12-131-18/+0Star
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-131-1/+1
* target/mips: Remove mips_def_t unused argument from mvp_init()Philippe Mathieu-Daudé2020-12-131-1/+1
* target/mips: Remove unused headers from translate.cPhilippe Mathieu-Daudé2020-12-131-2/+0Star
* hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-131-2/+0Star
* target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-131-2/+2
* target/mips: Add unaligned access support for MIPS64R6 and Loongson-3Huacai Chen2020-11-031-2/+2
* target/mips: Fix Lesser GPL version numberChetan Pant2020-11-031-1/+1
* target/mips: Add loongson-ext lsdc2 group of instructionsJiaxun Yang2020-10-171-0/+179
* target/mips: Add loongson-ext lswc2 group of instructions (Part 2)Jiaxun Yang2020-10-171-2/+180
* target/mips: Add loongson-ext lswc2 group of instructions (Part 1)Jiaxun Yang2020-10-171-0/+86
* target/mips: Fix some comment spelling errorszhaolichang2020-10-171-5/+5
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