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* target/mips: Fix RDHWR CC with icountJames Hogan2017-08-021-0/+11
* target/mips: Drop redundant gen_io_start/stop()James Hogan2017-08-021-8/+0Star
* target/mips: Use BS_EXCP where interrupts are expectedJames Hogan2017-08-021-13/+34
* target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae2017-08-021-2/+3
* mips: Add KVM T&E segment support for TCGJames Hogan2017-08-022-4/+4
* mips: Improve segment defs for KVM T&E guestsJames Hogan2017-08-021-12/+11Star
* target-mips: Don't stop on [d]mtc0 DESAVE/KScratchJames Hogan2017-08-021-4/+0Star
* docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé2017-07-311-1/+1
* target/mips: Enable CP0_EBase.WG on MIPS64 CPUsJames Hogan2017-07-211-0/+2
* target/mips: Add EVA support to P5600James Hogan2017-07-211-6/+8
* target/mips: Implement segmentation controlJames Hogan2017-07-201-39/+152
* target/mips: Add segmentation control registersJames Hogan2017-07-205-2/+150
* target/mips: Add an MMU mode for ERLJames Hogan2017-07-202-4/+23
* target/mips: Abstract mmu_idx from hflagsJames Hogan2017-07-203-4/+10
* target/mips: Check memory permissions with mem_idxJames Hogan2017-07-201-8/+9
* target/mips: Decode microMIPS EVA load & store instructionsJames Hogan2017-07-201-4/+115
* target/mips: Decode MIPS32 EVA load & store instructionsJames Hogan2017-07-201-0/+106
* target/mips: Prepare loads/stores for EVAJames Hogan2017-07-201-35/+42
* target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan2017-07-206-15/+31
* target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan2017-07-202-2/+2
* target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan2017-07-201-2/+10
* target/mips: Fix MIPS64 MFC0 UserLocal on BE hostJames Hogan2017-07-201-2/+3
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno2017-07-171-6/+12
* mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk2017-07-171-0/+2
* target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic2017-07-111-2/+6
* vcpu_dirty: share the same field in CPUState for all acceleratorsSergio Andres Gomez Del Real2017-07-041-2/+2
* target/mips: optimize indirect branchesAurelien Jarno2017-06-051-1/+1
* target/mips: optimize cross-page direct jumps in softmmuAurelien Jarno2017-06-051-1/+1
* target/mips: fix delay slot detection in gen_msa_branch()Yongbok Kim2017-03-201-1/+1
* target-mips: replace few LOG_DISAS() with trace pointsPhilippe Mathieu-Daudé2017-03-202-14/+16
* target-mips: replace break by goto cp0_unimplementedPhilippe Mathieu-Daudé2017-03-201-44/+44
* target-mips: log bad coprocessor0 register accesses with LOG_UNIMPPhilippe Mathieu-Daudé2017-03-201-6/+6
* target-mips: remove old & unuseful commentsPhilippe Mathieu-Daudé2017-03-201-4/+0Star
* target-mips: fix compiler warnings (clang 5)Philippe Mathieu-Daudé2017-03-201-4/+12
* target/mips: hold BQL for timer interruptsYongbok Kim2017-03-091-3/+18
* KVM: do not use sigtimedwait to catch SIGBUSPaolo Bonzini2017-03-031-6/+0Star
* KVM: remove kvm_arch_on_sigbusPaolo Bonzini2017-03-031-6/+0Star
* target-mips: Provide function to test if a CPU supports an ISAPaul Burton2017-02-212-0/+11
* migration: extend VMStateInfoJianjun Duan2017-01-241-4/+10
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2017-01-201-0/+5
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| * stubs: remove stubs/kvm.cPaolo Bonzini2017-01-161-0/+5
* | cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-133-8/+8
* | qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-132-2/+4
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* target-mips: Use clz opcodeRichard Henderson2017-01-103-36/+16Star
* target-mips: Use the new extract opRichard Henderson2017-01-101-7/+5Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-2019-0/+38839