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* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-253-7/+7
* mips: Tweak location of ';' in macrosEric Blake2018-01-161-16/+18
* tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson2017-12-291-1/+1
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2017-10-304-29/+13Star
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| * mips: malta/boston: replace cpu_model with cpu_typeIgor Mammedov2017-10-274-29/+13Star
* | Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Avoid setting tcg_initialize if !CONFIG_TCGRichard Henderson2017-10-261-0/+2
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-4/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-13/+13
* | qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-242-11/+1Star
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* linux-user: Tidy and enforce reserved_va initializationRichard Henderson2017-10-161-1/+5
* tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota2017-10-101-2/+2
* qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé2017-10-101-4/+0Star
* mips: Improve macro parenthesizationEric Blake2017-09-211-28/+28
* mips: replace cpu_mips_init() with cpu_generic_init()Igor Mammedov2017-09-212-19/+1Star
* mips: MIPSCPU model subclassesIgor Mammedov2017-09-215-64/+117
* mips: call cpu_mips_realize_env() from mips_cpu_realizefn()Philippe Mathieu-Daudé2017-09-212-1/+3
* mips: split cpu_mips_realize_env() out of cpu_mips_init()Philippe Mathieu-Daudé2017-09-212-7/+13
* mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé2017-09-2111-353/+372
* mips: move hw/mips/cputimer.c to target/mips/Philippe Mathieu-Daudé2017-09-212-1/+165
* target/mips: Convert VM clock update prints to warn_reportAlistair Francis2017-09-191-3/+3
* Convert single line fprintf(.../n) to warn_report()Alistair Francis2017-09-191-2/+2
* target/mips: Fix RDHWR CC with icountJames Hogan2017-08-021-0/+11
* target/mips: Drop redundant gen_io_start/stop()James Hogan2017-08-021-8/+0Star
* target/mips: Use BS_EXCP where interrupts are expectedJames Hogan2017-08-021-13/+34
* target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae2017-08-021-2/+3
* mips: Add KVM T&E segment support for TCGJames Hogan2017-08-022-4/+4
* mips: Improve segment defs for KVM T&E guestsJames Hogan2017-08-021-12/+11Star
* target-mips: Don't stop on [d]mtc0 DESAVE/KScratchJames Hogan2017-08-021-4/+0Star
* docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé2017-07-311-1/+1
* target/mips: Enable CP0_EBase.WG on MIPS64 CPUsJames Hogan2017-07-211-0/+2
* target/mips: Add EVA support to P5600James Hogan2017-07-211-6/+8
* target/mips: Implement segmentation controlJames Hogan2017-07-201-39/+152
* target/mips: Add segmentation control registersJames Hogan2017-07-205-2/+150
* target/mips: Add an MMU mode for ERLJames Hogan2017-07-202-4/+23
* target/mips: Abstract mmu_idx from hflagsJames Hogan2017-07-203-4/+10
* target/mips: Check memory permissions with mem_idxJames Hogan2017-07-201-8/+9
* target/mips: Decode microMIPS EVA load & store instructionsJames Hogan2017-07-201-4/+115
* target/mips: Decode MIPS32 EVA load & store instructionsJames Hogan2017-07-201-0/+106
* target/mips: Prepare loads/stores for EVAJames Hogan2017-07-201-35/+42
* target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan2017-07-206-15/+31
* target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan2017-07-202-2/+2
* target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan2017-07-201-2/+10
* target/mips: Fix MIPS64 MFC0 UserLocal on BE hostJames Hogan2017-07-201-2/+3
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno2017-07-171-6/+12
* mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk2017-07-171-0/+2
* target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic2017-07-111-2/+6
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