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* target/mips: Replace GET_LMASK() macro by get_lmask(32) functionPhilippe Mathieu-Daudé2021-08-251-11/+21
* target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpersPhilippe Mathieu-Daudé2021-08-251-22/+33
* target/mips: Define gen_helper() macros in translate.hPhilippe Mathieu-Daudé2021-08-252-12/+12
* target/mips: Use tcg_constant_i32() in generate_exception_err()Philippe Mathieu-Daudé2021-08-251-5/+2Star
* target/mips: Inline gen_helper_0e0i()Philippe Mathieu-Daudé2021-08-251-6/+2Star
* target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macrosPhilippe Mathieu-Daudé2021-08-251-5/+1Star
* target/mips: Simplify gen_helper() macros by using tcg_constant_i32()Philippe Mathieu-Daudé2021-08-251-15/+5Star
* target/mips: Use tcg_constant_i32() in gen_helper_0e2i()Philippe Mathieu-Daudé2021-08-251-12/+2Star
* target/mips: Remove gen_helper_1e2i()Philippe Mathieu-Daudé2021-08-251-6/+0Star
* target/mips: Remove gen_helper_0e3i()Philippe Mathieu-Daudé2021-08-251-6/+0Star
* target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXTPhilippe Mathieu-Daudé2021-08-251-2/+0Star
* target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddrPhilippe Mathieu-Daudé2021-08-251-1/+1
* target/mips: Document Loongson-3A CPU definitionsPhilippe Mathieu-Daudé2021-08-251-2/+2
* target/mips: Convert Vr54xx MSA* opcodes to decodetreePhilippe Mathieu-Daudé2021-08-253-53/+14Star
* target/mips: Convert Vr54xx MUL* opcodes to decodetreePhilippe Mathieu-Daudé2021-08-253-24/+18Star
* target/mips: Convert Vr54xx MACC* opcodes to decodetreePhilippe Mathieu-Daudé2021-08-253-16/+42
* target/mips: Introduce decodetree structure for NEC Vr54xx extensionPhilippe Mathieu-Daudé2021-08-255-0/+33
* target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.cPhilippe Mathieu-Daudé2021-08-253-118/+143
* target/mips: Extract NEC Vr54xx helper definitionsPhilippe Mathieu-Daudé2021-08-252-15/+27
* target/mips: Introduce generic TRANS() macro for decodetree helpersPhilippe Mathieu-Daudé2021-08-251-0/+8
* target/mips: Rename 'rtype' as 'r'Philippe Mathieu-Daudé2021-08-256-46/+46
* target/mips: Merge 32-bit/64-bit Release6 decodetree definitionsPhilippe Mathieu-Daudé2021-08-254-40/+19Star
* target/mips: Decode vendor extensions before MIPS ISAsPhilippe Mathieu-Daudé2021-08-251-3/+5
* target/mips: Simplify PREF opcodePhilippe Mathieu-Daudé2021-08-251-6/+2Star
* target/mips: Remove JR opcode unused argumentsPhilippe Mathieu-Daudé2021-08-251-1/+1
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-19/+0Star
* Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into stagingPeter Maydell2021-07-124-29/+427
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| * target/mips: Rewrite UHI errno_mips() using switch statementPhilippe Mathieu-Daudé2021-07-111-15/+9Star
| * target/mips/tx79: Introduce SQ opcode (Store Quadword)Philippe Mathieu-Daudé2021-07-112-0/+28
| * target/mips/tx79: Introduce LQ opcode (Load Quadword)Philippe Mathieu-Daudé2021-07-113-14/+45
| * target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)Philippe Mathieu-Daudé2021-07-112-0/+29
| * target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)Philippe Mathieu-Daudé2021-07-112-0/+31
| * target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)Philippe Mathieu-Daudé2021-07-112-0/+21
| * target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)Philippe Mathieu-Daudé2021-07-112-0/+69
| * target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)Philippe Mathieu-Daudé2021-07-112-0/+78
| * target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)Philippe Mathieu-Daudé2021-07-112-0/+34
| * target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)Philippe Mathieu-Daudé2021-07-112-0/+25
| * target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)Philippe Mathieu-Daudé2021-07-112-0/+58
* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-121-17/+4Star
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| * | target/mips: Fix missing else in gen_goto_tbRichard Henderson2021-07-091-1/+2
| * | target/mips: Use translator_use_goto_tbRichard Henderson2021-07-091-15/+2Star
| * | tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
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* / meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+6
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* target/mips: Extract nanoMIPS ISA translation routinesPhilippe Mathieu-Daudé2021-07-022-4922/+4924
* target/mips: Extract the microMIPS ISA translation routinesPhilippe Mathieu-Daudé2021-07-022-3225/+3237
* target/mips: Extract Code Compaction ASE translation routinesPhilippe Mathieu-Daudé2021-07-022-1117/+1129
* target/mips: Add declarations for generic TCG helpersPhilippe Mathieu-Daudé2021-07-022-5/+9
* target/mips: Fix gen_mxu_s32ldd_s32lddrRichard Henderson2021-06-291-5/+1Star
* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-291-1/+1
* target/mips: Merge msa32/msa64 decodetree definitionsPhilippe Mathieu-Daudé2021-06-244-32/+10Star
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