| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/mips: Amend MXU ASE overview note | Aleksandar Markovic | 2018-10-29 | 1 | -10/+74 |
| * | target/mips: Move MXU_EN check one level higher | Aleksandar Markovic | 2018-10-29 | 1 | -271/+238 |
| * | target/mips: Add emulation of MXU instructions S32LDD and S32LDDR | Craig Janeczek | 2018-10-29 | 1 | -7/+47 |
| * | target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU | Craig Janeczek | 2018-10-29 | 1 | -7/+94 |
| * | target/mips: Add emulation of MXU instruction D16MAC | Craig Janeczek | 2018-10-29 | 1 | -3/+87 |
| * | target/mips: Add emulation of MXU instruction D16MUL | Craig Janeczek | 2018-10-29 | 1 | -3/+63 |
| * | target/mips: Add emulation of MXU instruction S8LDD | Craig Janeczek | 2018-10-29 | 1 | -3/+87 |
| * | target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch | Aleksandar Markovic | 2018-10-29 | 1 | -18/+23 |
| * | target/mips: Add emulation of MXU instructions S32I2M and S32M2I | Craig Janeczek | 2018-10-29 | 1 | -6/+85 |
| * | target/mips: Add emulation of non-MXU MULL within MXU decoding engine | Craig Janeczek | 2018-10-29 | 1 | -1/+18 |
| * | target/mips: Add bit encoding for MXU operand getting pattern 'optn3' | Craig Janeczek | 2018-10-29 | 1 | -0/+10 |
| * | target/mips: Add bit encoding for MXU operand getting pattern 'optn2' | Craig Janeczek | 2018-10-29 | 1 | -0/+6 |
| * | target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' | Aleksandar Markovic | 2018-10-29 | 1 | -0/+6 |
| * | target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' | Craig Janeczek | 2018-10-29 | 1 | -0/+6 |
| * | target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' | Aleksandar Markovic | 2018-10-29 | 1 | -0/+6 |
| * | target/mips: Add MXU decoding engine | Aleksandar Markovic | 2018-10-29 | 1 | -2/+1141 |
| * | target/mips: Add and integrate MXU decoding engine placeholder | Aleksandar Markovic | 2018-10-29 | 1 | -0/+8 |
| * | target/mips: Amend MXU instruction opcodes | Aleksandar Markovic | 2018-10-29 | 1 | -91/+69 |
| * | target/mips: Define a bit for MXU in insn_flags | Craig Janeczek | 2018-10-29 | 1 | -0/+1 |
| * | target/mips: Introduce MXU registers | Craig Janeczek | 2018-10-29 | 2 | -0/+30 |
| * | target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases | Aleksandar Markovic | 2018-10-29 | 1 | -0/+2 |
| * | target/mips: Add disassembler support for nanoMIPS | Aleksandar Markovic | 2018-10-25 | 1 | -2/+11 |
| * | target/mips: Implement emulation of nanoMIPS EVA instructions | Dimitrije Nikolic | 2018-10-25 | 1 | -0/+128 |
| * | target/mips: Add nanoMIPS CRC32 instruction pool | Aleksandar Markovic | 2018-10-25 | 1 | -0/+10 |
| * | target/mips: Fix decoding of ALIGN and DALIGN instructions | Aleksandar Markovic | 2018-10-24 | 1 | -8/+32 |
| * | target/mips: Fix the title of translate.c | Aleksandar Markovic | 2018-10-24 | 1 | -1/+1 |
| * | target/mips: Define the R5900 CPU | Fredrik Noring | 2018-10-24 | 1 | -0/+59 |
| * | target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only | Fredrik Noring | 2018-10-24 | 1 | -1/+22 |
| * | target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV | Fredrik Noring | 2018-10-24 | 1 | -2/+3 |
| * | target/mips: Support R5900 DIV1 and DIVU1 instructions | Fredrik Noring | 2018-10-24 | 1 | -3/+9 |
| * | target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions | Fredrik Noring | 2018-10-24 | 1 | -6/+17 |
| * | target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions | Fredrik Noring | 2018-10-24 | 1 | -3/+14 |
| * | target/mips: Support R5900 three-operand MULT and MULTU instructions | Fredrik Noring | 2018-10-24 | 1 | -0/+74 |
| * | target/mips: Add a placeholder for R5900 MMI3 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+30 |
| * | target/mips: Add a placeholder for R5900 MMI2 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+39 |
| * | target/mips: Add a placeholder for R5900 MMI1 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+35 |
| * | target/mips: Add a placeholder for R5900 MMI0 instruction subclass | Fredrik Noring | 2018-10-24 | 1 | -1/+42 |
| * | target/mips: Add a placeholder for R5900 MMI instruction class | Fredrik Noring | 2018-10-24 | 1 | -1/+44 |
| * | target/mips: Add a placeholder for R5900 LQ | Fredrik Noring | 2018-10-24 | 1 | -2/+11 |
| * | target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR | Fredrik Noring | 2018-10-24 | 1 | -1/+52 |
| * | target/mips: Define R5900 MMI3 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+39 |
| * | target/mips: Define R5900 MMI2 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+48 |
| * | target/mips: Define R5900 MMI1 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+44 |
| * | target/mips: Define R5900 MMI0 opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+51 |
| * | target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+51 |
| * | target/mips: Define R5900 MMI class, and LQ and SQ opcode constants | Fredrik Noring | 2018-10-24 | 1 | -0/+40 |
| * | target/mips: Add R5900 Multimedia Instruction overview note | Fredrik Noring | 2018-10-24 | 1 | -0/+161 |
| * | target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants | Fredrik Noring | 2018-10-24 | 1 | -0/+3 |
| * | target/mips: Add opcodes for nanoMIPS EVA instructions | Dimitrije Nikolic | 2018-10-18 | 1 | -0/+34 |
| * | target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH | Stefan Markovic | 2018-10-18 | 1 | -1/+1 |
