| Commit message (Expand) | Author | Age | Files | Lines |
* | target/openrisc: Support non-busy idle state using PMR SPR | Stafford Horne | 2017-05-04 | 1 | -0/+2 |
* | target/openrisc: Implement EPH bit | Tim 'mithro' Ansell | 2017-04-21 | 1 | -0/+3 |
* | target/openrisc: Implement EVBAR register | Tim 'mithro' Ansell | 2017-04-21 | 1 | -1/+5 |
* | target/openrisc: Tidy handling of delayed branches | Richard Henderson | 2017-02-13 | 1 | -2/+2 |
* | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 2017-02-13 | 1 | -1/+1 |
* | target/openrisc: Implement lwa, swa | Richard Henderson | 2017-02-13 | 1 | -0/+1 |
* | target/openrisc: Fix exception handling status registers | Stafford Horne | 2017-02-13 | 1 | -0/+7 |
* | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 2017-01-13 | 1 | -1/+1 |
* | Move target-* CPU file into a target/ folder | Thomas Huth | 2016-12-20 | 1 | -0/+87 |