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path: root/target/openrisc/sys_helper.c
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* target/openrisc: Use env_cpu, env_archcpuRichard Henderson2019-06-101-4/+4
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* target/openrisc: Fix writes to interrupt mask registerStafford Horne2018-07-031-1/+1
* target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson2018-07-021-8/+8
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Fix tlb flushing in mtsprRichard Henderson2018-07-021-6/+15
* target/openrisc: Reduce tlb to a single dimensionRichard Henderson2018-07-021-10/+10
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-021-15/+0Star
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-021-14/+14
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-021-6/+3Star
* target/openrisc: Fix mtspr shadow gprsRichard Henderson2018-07-021-0/+1
* icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk2018-04-111-4/+4
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-201-2/+2
* target/openrisc: Make coreid and numcores variableStafford Horne2017-10-201-2/+3
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+13
* target/openrisc: implement shadow registersStafford Horne2017-05-041-0/+9
* target/openrisc: add numcores and coreid supportStafford Horne2017-05-041-0/+6
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-0/+7
* target/openrisc: Tidy handling of delayed branchesRichard Henderson2017-02-131-1/+1
* target/openrisc: Tidy ppc/npc implementationRichard Henderson2017-02-131-28/+16Star
* target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson2017-02-131-0/+13
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-131-3/+2Star
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-1/+1
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+288