summaryrefslogtreecommitdiffstats
path: root/target/openrisc/translate.c
Commit message (Expand)AuthorAgeFilesLines
* target/openrisc: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-10/+0Star
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+4
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
* target/openrisc: Drop checks for singlestep_enabledRichard Henderson2021-10-161-15/+3Star
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-1/+1
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
* target/openrisc: Use dc->zero in gen_add, gen_addcRichard Henderson2021-07-131-5/+5
* target/openrisc: Cache constant 0 in DisasContextRichard Henderson2021-07-131-6/+6
* target/openrisc: Use tcg_constant_tl for dc->R0Richard Henderson2021-07-131-8/+2Star
* target/openrisc: Use tcg_constant_*Richard Henderson2021-07-131-33/+9Star
* target/openrisc: Use translator_use_goto_tbRichard Henderson2021-07-091-7/+8
* tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
* target/openrisc: fix icount handling for timer instructionsPavel Dovgalyuk2021-04-011-0/+15
* meson: targetPaolo Bonzini2020-08-211-1/+1
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/openrisc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* target/openrisc: Implement l.adrpRichard Henderson2019-09-041-0/+13
* target/openrisc: Implement unordered fp comparisonsRichard Henderson2019-09-041-0/+85
* target/openrisc: Add support for ORFPX64A32Richard Henderson2019-09-041-0/+230
* target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2019-09-041-49/+35Star
* target/openrisc: Cache R0 in DisasContextRichard Henderson2019-09-041-7/+12
* target/openrisc: Replace cpu register array with a functionRichard Henderson2019-09-041-97/+116
* target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson2019-09-041-47/+49
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-2/+2
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-6/+5Star
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-311-100/+100
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-021-1/+1
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-021-7/+9
* target/openrisc: Exit the TB after l.mtsprRichard Henderson2018-07-021-1/+16
* target/openrisc: Split out is_userRichard Henderson2018-07-021-15/+12Star
* target/openrisc: Link more translation blocksRichard Henderson2018-07-021-41/+55
* target/openrisc: Fix singlestep_enabledRichard Henderson2018-07-021-18/+17Star
* target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2018-07-021-3/+3
* target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-021-114/+0Star
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
* target/openrisc: Merge disas_openrisc_insnRichard Henderson2018-05-141-9/+4Star
* target/openrisc: Convert dec_floatRichard Henderson2018-05-141-230/+128Star
* target/openrisc: Convert dec_compiRichard Henderson2018-05-141-58/+58
* target/openrisc: Convert dec_compRichard Henderson2018-05-141-62/+58Star
* target/openrisc: Convert dec_MRichard Henderson2018-05-141-28/+13Star
* target/openrisc: Convert dec_logicRichard Henderson2018-05-141-36/+26Star
* target/openrisc: Convert dec_macRichard Henderson2018-05-141-33/+22Star
* target/openrisc: Convert dec_calcRichard Henderson2018-05-141-149/+173
* target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2018-05-141-149/+110Star
* target/openrisc: Convert memory insnsRichard Henderson2018-05-141-139/+136Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-16 16:35:11 +0200