bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	2017-05-04	5	-1/+28
*	target/openrisc: Remove duplicate features property	Stafford Horne	2017-05-04	2	-28/+5
*	target/openrisc: Implement full vmstate serialization	Stafford Horne	2017-05-04	1	-2/+71
*	target/openrisc: implement shadow registers	Stafford Horne	2017-05-04	6	-10/+33
*	target/openrisc: add numcores and coreid support	Stafford Horne	2017-05-04	1	-0/+6
*	target/openrisc: Fixes for memory debugging	Stafford Horne	2017-05-04	1	-4/+20
*	target/openrisc: Implement EPH bit	Tim 'mithro' Ansell	2017-04-21	1	-0/+3
*	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	2017-04-21	4	-1/+21
*	target/openrisc: Optimize for r0 being zero	Richard Henderson	2017-02-13	3	-23/+66
*	target/openrisc: Tidy handling of delayed branches	Richard Henderson	2017-02-13	5	-35/+25
*	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	2017-02-13	6	-55/+39
*	target/openrisc: Optimize l.jal to next	Richard Henderson	2017-02-13	1	-1/+5
*	target/openrisc: Fix madd	Richard Henderson	2017-02-13	4	-61/+30
*	target/openrisc: Implement muld, muldu, macu, msbu	Richard Henderson	2017-02-13	1	-0/+108
*	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	2017-02-13	4	-61/+80
*	target/openrisc: Implement msync	Richard Henderson	2017-02-13	1	-0/+1
*	target/openrisc: Enable trap, csync, msync, psync for user mode	Richard Henderson	2017-02-13	1	-32/+0
*	target/openrisc: Set flags on helpers	Richard Henderson	2017-02-13	1	-12/+12
*	target/openrisc: Use movcond where appropriate	Richard Henderson	2017-02-13	1	-14/+14
*	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson	2017-02-13	4	-89/+78
*	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	2017-02-13	7	-74/+96
*	target/openrisc: Invert the decoding in dec_calc	Richard Henderson	2017-02-13	1	-207/+95
*	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	2017-02-13	3	-12/+18
*	target/openrisc: Streamline arithmetic and OVE	Richard Henderson	2017-02-13	5	-314/+191
*	target/openrisc: Rationalize immediate extraction	Richard Henderson	2017-02-13	1	-58/+40
*	target/openrisc: Tidy insn dumping	Richard Henderson	2017-02-13	1	-24/+12
*	target/openrisc: Implement lwa, swa	Richard Henderson	2017-02-13	7	-8/+81
*	target/openrisc: Fix exception handling status registers	Stafford Horne	2017-02-13	1	-0/+7
*	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson	2017-02-13	1	-1/+1
*	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	2017-01-13	3	-3/+3
*	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	2017-01-13	2	-8/+4
*	target-openrisc: Use clz and ctz opcodes	Richard Henderson	2017-01-10	3	-23/+4
*	Move target-* CPU file into a target/ folder	Thomas Huth	2016-12-20	17	-0/+3868