| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode | Richard Henderson | 2021-06-19 | 1 | -3/+0 |
| * | target/ppc: Implement cfuged instruction | Matheus Ferst | 2021-06-03 | 1 | -0/+1 |
| * | target/ppc: Mark helper_raise_exception* as noreturn | Richard Henderson | 2021-05-19 | 1 | -2/+2 |
| * | target/ppc: Create helper_scv | Richard Henderson | 2021-05-04 | 1 | -0/+1 |
| * | target/ppc: add vmulh{su}d instructions | Lijun Pan | 2020-08-12 | 1 | -0/+2 |
| * | target/ppc: add vmulh{su}w instructions | Lijun Pan | 2020-08-12 | 1 | -0/+2 |
| * | target/ppc: convert vmuluwm to tcg_gen_gvec_mul | Lijun Pan | 2020-08-12 | 1 | -1/+0 |
| * | target/ppc: Use tcg_gen_gvec_rotlv | Richard Henderson | 2020-06-02 | 1 | -4/+0 |
| * | target/ppc: Add support for scv and rfscv instructions | Nicholas Piggin | 2020-05-27 | 1 | -0/+1 |
| * | target/ppc: Fix ISA v3.0 (POWER9) slbia implementation | Nicholas Piggin | 2020-03-24 | 1 | -1/+1 |
| * | target/ppc: Add privileged message send facilities | Cédric Le Goater | 2020-02-02 | 1 | -0/+4 |
| * | target/ppc: Add SPR TBU40 | Suraj Jitindar Singh | 2019-12-17 | 1 | -0/+1 |
| * | target/ppc: Work [S]PURR implementation and add HV support | Suraj Jitindar Singh | 2019-12-17 | 1 | -0/+1 |
| * | target/ppc: Implement the VTB for HV access | Suraj Jitindar Singh | 2019-12-17 | 1 | -0/+2 |
| * | target/ppc: update {get,set}_dfp{64,128}() helper functions to read/write DFP... | Mark Cave-Ayland | 2019-10-04 | 1 | -1/+1 |
| * | target/ppc: Optimize emulation of vclzw instruction | Stefan Brankovic | 2019-08-21 | 1 | -1/+0 |
| * | target/ppc: Optimize emulation of vclzd instruction | Stefan Brankovic | 2019-08-21 | 1 | -1/+0 |
| * | target/ppc: Optimize emulation of vgbbd instruction | Stefan Brankovic | 2019-08-21 | 1 | -1/+0 |
| * | target/ppc: Optimize emulation of vsl and vsr instructions | Stefan Brankovic | 2019-08-21 | 1 | -2/+0 |
| * | target/ppc: Optimize emulation of lvsl and lvsr instructions | Stefan Brankovic | 2019-08-21 | 1 | -2/+0 |
| * | target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro | Mark Cave-Ayland | 2019-07-02 | 1 | -32/+16 |
| * | target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time | Mark Cave-Ayland | 2019-07-02 | 1 | -2/+2 |
| * | target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at transla... | Mark Cave-Ayland | 2019-07-02 | 1 | -4/+4 |
| * | target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -3/+3 |
| * | target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -10/+10 |
| * | target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -8/+8 |
| * | target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -4/+4 |
| * | target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -6/+6 |
| * | target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -60/+60 |
| * | target/ppc: introduce separate generator and helper for xscvqpdp | Mark Cave-Ayland | 2019-07-02 | 1 | -1/+1 |
| * | target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c | Mark Cave-Ayland | 2019-07-02 | 1 | -60/+60 |
| * | target/ppc: introduce separate VSX_CMP macro for xvcmp* instructions | Mark Cave-Ayland | 2019-07-02 | 1 | -8/+12 |
| * | target/ppc: Use vector variable shifts for VSL, VSR, VSRA | Richard Henderson | 2019-05-29 | 1 | -12/+0 |
| * | target/ppc: Flush the TLB locally when the LPIDR is written | Benjamin Herrenschmidt | 2019-02-25 | 1 | -0/+1 |
| * | target/ppc: convert vmin* and vmax* to vector operations | Richard Henderson | 2019-02-18 | 1 | -16/+0 |
| * | target/ppc: convert vadd*s and vsub*s to vector operations | Richard Henderson | 2019-02-18 | 1 | -12/+12 |
| * | target/ppc: Add helper_mfvscr | Richard Henderson | 2019-02-18 | 1 | -0/+1 |
| * | target/ppc: Pass integer to helper_mtvscr | Richard Henderson | 2019-02-18 | 1 | -1/+1 |
| * | target/ppc: convert vsplt[bhw] to use vector operations | Richard Henderson | 2019-02-18 | 1 | -3/+0 |
| * | target/ppc: convert vspltis[bhw] to use vector operations | Richard Henderson | 2019-02-18 | 1 | -3/+0 |
| * | target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector oper... | Mark Cave-Ayland | 2019-02-18 | 1 | -8/+0 |
| * | target/ppc: add external PID support | Roman Kapl | 2018-11-08 | 1 | -0/+4 |
| * | target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 | Richard Henderson | 2018-10-19 | 1 | -1/+1 |
| * | target/ppc: Use non-arithmetic conversions for fp load/store | Richard Henderson | 2018-08-21 | 1 | -2/+2 |
| * | target/ppc: Tidy helper_fsqrt | Richard Henderson | 2018-08-21 | 1 | -1/+1 |
| * | target/ppc: Tidy helper_fadd, helper_fsub | Richard Henderson | 2018-08-21 | 1 | -2/+2 |
| * | target/ppc: Tidy helper_fmul | Richard Henderson | 2018-08-21 | 1 | -1/+1 |
| * | target/ppc: Honor fpscr_ze semantics and tidy fdiv | Richard Henderson | 2018-08-21 | 1 | -1/+1 |
| * | target/ppc: Use atomic cmpxchg for STQCX | Richard Henderson | 2018-07-03 | 1 | -0/+2 |
| * | target/ppc: Use atomic store for STQ | Richard Henderson | 2018-07-03 | 1 | -0/+4 |
