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* target/ppc: implement plxsd/pstxsdLeandro Lupori2022-03-021-2/+53
* target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructionsVíctor Colombo2022-03-021-1/+30
* target/ppc: Implement xs{max,min}cqpVíctor Colombo2022-03-021-0/+2
* target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3Víctor Colombo2022-03-021-26/+4Star
* target/ppc: Move xscmp{eq,ge,gt}dp to decodetreeVíctor Colombo2022-03-022-6/+25
* target/ppc: Implement xscmp{eq,ge,gt}qpVíctor Colombo2022-03-021-0/+31
* target/ppc: Remove xscmpnedp instructionVíctor Colombo2022-03-022-2/+0Star
* target/ppc: Implement xvtlsbb instructionVíctor Colombo2022-03-021-0/+40
* target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]Matheus Ferst2022-03-021-0/+25
* target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetreeMatheus Ferst2022-03-022-24/+48
* target/ppc: Implement xxgenpcv[bhwd]m instructionMatheus Ferst2022-03-021-0/+43
* target/ppc: Implement xxevalMatheus Ferst2022-03-021-0/+220
* target/ppc: Implement xxpermx instructionMatheus Ferst2022-03-021-0/+22
* target/ppc: Move xxpermdi to decodetreeMatheus Ferst2022-03-022-41/+32Star
* target/ppc: move xxperm/xxpermr to decodetreeMatheus Ferst2022-03-022-4/+40
* target/ppc: Move xxsel to decodetreeMatheus Ferst2022-03-022-55/+8Star
* target/ppc: Move vsel and vperm/vpermr to decodetreeMatheus Ferst2022-03-022-18/+53
* target/ppc: implement vrlqmiMatheus Ferst2022-03-021-4/+17
* target/ppc: implement vrlqnmMatheus Ferst2022-03-021-5/+76
* target/ppc: implement vrlqMatheus Ferst2022-03-021-0/+48
* target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetreeMatheus Ferst2022-03-022-10/+147
* target/ppc: move vrl[bhwd] to decodetreeMatheus Ferst2022-03-022-12/+7Star
* target/ppc: implement vsraqMatheus Ferst2022-03-021-6/+17
* target/ppc: implement vsrqMatheus Ferst2022-03-021-10/+30
* target/ppc: implement vslqMatheus Ferst2022-03-021-0/+40
* target/ppc: move vs[lr][a][bhwd] to decodetreeMatheus Ferst2022-03-022-26/+28
* target/ppc: implement vgnbMatheus Ferst2022-03-021-0/+135
* target/ppc: implement vcntmb[bhwd]Matheus Ferst2022-03-021-0/+32
* target/ppc: implement vclrrbMatheus Ferst2022-03-021-8/+24
* target/ppc: implement vclrlbMatheus Ferst2022-03-021-0/+40
* target/ppc: implement vstri[bh][lr]Matheus Ferst2022-03-021-0/+30
* target/ppc: Implement Vector Compare QuadwordMatheus Ferst2022-03-021-0/+45
* target/ppc: Implement Vector Compare Greater Than QuadwordMatheus Ferst2022-03-021-0/+39
* target/ppc: Implement Vector Compare Equal QuadwordMatheus Ferst2022-03-021-0/+36
* target/ppc: Move Vector Compare Not Equal or Zero to decodetreeMatheus Ferst2022-03-022-7/+62
* target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetreeMatheus Ferst2022-03-022-40/+64
* target/ppc: Implement vextsd2qLucas Coutinho2022-03-021-0/+18
* target/ppc: Move vexts[bhw]2[wd] to decodetreeLucas Coutinho2022-03-022-10/+53
* target/ppc: Implement vmsumudm instructionVíctor Colombo2022-03-021-0/+34
* target/ppc: Implement vmsumcud instructionVíctor Colombo2022-03-021-0/+53
* target/ppc: vmulh* instructions without helpersLucas Mateus Castro (alqotel)2022-03-021-4/+87
* target/ppc: Moved vector multiply high and low to decodetreeLucas Mateus Castro (alqotel)2022-03-022-10/+16
* target/ppc: moved vector even and odd multiplication to decodetreeLucas Mateus Castro (alqotel)2022-03-022-30/+62
* target/ppc: Introduce TRANS*FLAGS macrosLuis Pires2022-03-021-25/+12Star
* target/ppc: Change VSX instructions behavior to fill with zerosVíctor Colombo2022-02-091-1/+3
* target/ppc: Remove PowerPC 601 CPUsCédric Le Goater2022-02-091-179/+0Star
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-083-34/+34
* PPC64/TCG: Implement 'rfebb' instructionDaniel Henrique Barboza2021-12-171-0/+33
* target/ppc: move xscvqpdp to decodetreeMatheus Ferst2021-12-172-12/+13
* target/ppc: fix xscvqpdp register accessMatheus Ferst2021-12-171-2/+3
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-21 04:51:28 +0100