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* PPC64/TCG: Implement 'rfebb' instructionDaniel Henrique Barboza2021-12-176-0/+85
* target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) eventDaniel Henrique Barboza2021-12-175-4/+42
* target/ppc: enable PMU instruction countDaniel Henrique Barboza2021-12-177-1/+146
* target/ppc: enable PMU counter overflow with cycle eventsDaniel Henrique Barboza2021-12-172-0/+73
* target/ppc: PMU: update counters on MMCR1 writeDaniel Henrique Barboza2021-12-175-1/+21
* target/ppc: PMU: update counters on PMCs r/wDaniel Henrique Barboza2021-12-175-8/+51
* target/ppc: PMU basic cycle count for pseries TCGDaniel Henrique Barboza2021-12-176-4/+157
* target/ppc: introduce PMUEventType and PMU overflow timersDaniel Henrique Barboza2021-12-175-0/+127
* Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"Fabiano Rosas2021-12-171-9/+12
* target/ppc: Fix e6500 bootFabiano Rosas2021-12-172-1/+17
* target/ppc: move xscvqpdp to decodetreeMatheus Ferst2021-12-175-20/+21
* target/ppc: fix xscvqpdp register accessMatheus Ferst2021-12-171-2/+3
* target/ppc: Move xs{max,min}[cj]dp to decodetreeVictor Colombo2021-12-173-11/+40
* target/ppc: Fix xs{max, min}[cj]dp to use VSX registersVictor Colombo2021-12-173-10/+10
* target/ppc: remove 401/403 CPUsCédric Le Goater2021-12-177-608/+4Star
* target/ppc: Set 601v exception model idFabiano Rosas2021-12-171-0/+1
* target/ppc: Remove 603e exception modelFabiano Rosas2021-12-173-33/+2Star
* target/ppc: Fix MPCxxx FPU interrupt addressFabiano Rosas2021-12-171-2/+2
* target/ppc: Remove the software TLB model of 7450 CPUsFabiano Rosas2021-12-178-137/+6Star
* target/ppc: Disable unused facilities in the e600 CPUFabiano Rosas2021-12-171-5/+1Star
* target/ppc: Disable software TLB for the 7450 familyFabiano Rosas2021-12-171-15/+10Star
* target/ppc: Use helper_todouble/tosingle in helper_xststdcspRichard Henderson2021-12-171-11/+10Star
* target/ppc: Update fres to new flags and float64r32Richard Henderson2021-12-171-10/+10
* target/ppc: Add helper for frsqrtesRichard Henderson2021-12-173-2/+21
* target/ppc: Add helper for fmulsRichard Henderson2021-12-173-7/+17
* target/ppc: Add helpers for fadds, fsubs, fdivsRichard Henderson2021-12-173-7/+47
* target/ppc: Add helper for fsqrtsRichard Henderson2021-12-173-2/+14
* target/ppc: Add helpers for fmadds et alRichard Henderson2021-12-173-9/+25
* target/ppc: Update fre to new flagsRichard Henderson2021-12-171-13/+8Star
* target/ppc: Update xsrqpi and xsrqpxp to new flagsRichard Henderson2021-12-171-10/+5Star
* target/ppc: Update sqrt for new flagsRichard Henderson2021-12-171-47/+25Star
* target/ppc: Use helper_todouble in do_frspRichard Henderson2021-12-171-1/+1
* target/ppc: Update do_frsp for new flagsRichard Henderson2021-12-171-9/+4Star
* target/ppc: Split out do_frspRichard Henderson2021-12-171-11/+16
* target/ppc: Do not call do_float_check_status from do_fmaddRichard Henderson2021-12-171-5/+2Star
* target/ppc: Split out do_fmaddRichard Henderson2021-12-171-15/+18
* target/ppc: Update fmadd for new flagsRichard Henderson2021-12-171-35/+11Star
* target/ppc: Clean up do_friRichard Henderson2021-12-171-13/+11Star
* target/ppc: Tidy inexact handling in do_friRichard Henderson2021-12-171-5/+1Star
* target/ppc: Use FloatRoundMode in do_friRichard Henderson2021-12-171-1/+1
* target/ppc: Remove inline from do_friRichard Henderson2021-12-171-2/+2
* target/ppc: Fix VXCVI return valueRichard Henderson2021-12-171-12/+15
* target/ppc: Update float_invalid_cvt for new flagsRichard Henderson2021-12-171-9/+11
* target/ppc: Move float_check_status from FPU_FCTI to translateRichard Henderson2021-12-172-7/+5Star
* target/ppc: Update float_invalid_op_div for new flagsRichard Henderson2021-12-171-24/+14Star
* target/ppc: Update float_invalid_op_mul for new flagsRichard Henderson2021-12-171-16/+10Star
* target/ppc: Update float_invalid_op_addsub for new flagsRichard Henderson2021-12-171-24/+14Star
* target/ppc: Implement Vector Mask Move insnsMatheus Ferst2021-12-172-0/+126
* target/ppc: Implement Vector Extract MaskMatheus Ferst2021-12-172-0/+88
* target/ppc: Implement Vector Expand MaskMatheus Ferst2021-12-172-0/+45