summaryrefslogtreecommitdiffstats
path: root/target/riscv/cpu.h
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-221-3/+7
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-131-2/+6
|\
| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-2/+4
| * target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
| * target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-0/+1
* | Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* | Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* | Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
|/
* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-251-0/+2
* target/riscv: fix vill bit index in vtype registerFrank Chang2020-07-141-1/+1
* target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2020-07-021-1/+3
* target/riscv: add vector configure instructionLIU Zhiwei2020-07-021-9/+54
* target/riscv: implementation-defined constant parametersLIU Zhiwei2020-07-021-0/+5
* target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei2020-07-021-0/+12
* target/riscv: Add the lowRISC Ibex CPUAlistair Francis2020-06-031-0/+1
* target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-1/+0Star
* target/riscv: Remove the deprecated CPUsAlistair Francis2020-06-031-7/+0Star
* target/riscv: Add a sifive-e34 cpu typeCorey Wharton2020-04-291-0/+1
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-191-1/+1
|\
| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-1/+1
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
|/
* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-0/+5
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-271-0/+1
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+10
* target/riscv: Implement second stage MMUAlistair Francis2020-02-271-0/+1
* target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+11
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+2
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+4
* target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-271-0/+21
* target/riscv: Add the Hypervisor extensionAlistair Francis2020-02-271-0/+1
* target/riscv: Convert MIP CSR to target_ulongAlistair Francis2020-02-271-1/+1
* target/riscv: Fix tb->flags FS statusShihPo Hung2020-01-161-4/+1Star
* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-141-9/+0Star
* RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt2019-10-281-2/+5
* target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis2019-09-171-1/+1
* target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-171-1/+5
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* target/riscv: rationalise softfloat includesAlex Bennée2019-08-191-1/+1
* RISC-V: Add support for the Zicsr extensionPalmer Dabbelt2019-06-261-0/+1
* RISC-V: Add support for the Zifencei extensionPalmer Dabbelt2019-06-261-0/+1
* target/riscv: Add support for disabling/enabling CountersAlistair Francis2019-06-251-0/+1
* target/riscv: Remove user version informationAlistair Francis2019-06-251-2/+0Star
* target/riscv: Add the privledge spec version 1.11.0Alistair Francis2019-06-241-0/+1
* target/riscv: Restructure deprecatd CPUsAlistair Francis2019-06-241-6/+7
* RISC-V: Check PMP during Page Table WalksHesham Almatary2019-06-241-0/+1
* target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark2019-06-241-0/+2
* target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2019-06-241-0/+11
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-26 11:39:48 +0100