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path: root/target/riscv/cpu.h
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* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-0/+5
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-271-0/+1
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+10
* target/riscv: Implement second stage MMUAlistair Francis2020-02-271-0/+1
* target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+11
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+2
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+4
* target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-271-0/+21
* target/riscv: Add the Hypervisor extensionAlistair Francis2020-02-271-0/+1
* target/riscv: Convert MIP CSR to target_ulongAlistair Francis2020-02-271-1/+1
* target/riscv: Fix tb->flags FS statusShihPo Hung2020-01-161-4/+1Star
* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-141-9/+0Star
* RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt2019-10-281-2/+5
* target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis2019-09-171-1/+1
* target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-171-1/+5
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* target/riscv: rationalise softfloat includesAlex Bennée2019-08-191-1/+1
* RISC-V: Add support for the Zicsr extensionPalmer Dabbelt2019-06-261-0/+1
* RISC-V: Add support for the Zifencei extensionPalmer Dabbelt2019-06-261-0/+1
* target/riscv: Add support for disabling/enabling CountersAlistair Francis2019-06-251-0/+1
* target/riscv: Remove user version informationAlistair Francis2019-06-251-2/+0Star
* target/riscv: Add the privledge spec version 1.11.0Alistair Francis2019-06-241-0/+1
* target/riscv: Restructure deprecatd CPUsAlistair Francis2019-06-241-6/+7
* RISC-V: Check PMP during Page Table WalksHesham Almatary2019-06-241-0/+1
* target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark2019-06-241-0/+2
* target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2019-06-241-0/+11
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-3/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+1
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-2/+0Star
* target/riscv: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-1/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-17/+4Star
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-241-0/+2
* target/riscv: Create settable CPU propertiesAlistair Francis2019-05-241-0/+8
* target/riscv: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
* RISC-V: linux-user support for RVE ABIKito Cheng2019-03-191-0/+4
* RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-191-0/+2
* RISC-V: Add hooks to use the gdb xml files.Jim Wilson2019-03-191-0/+2
* RISC-V: Add debug support for accessing CSRs.Jim Wilson2019-03-191-0/+5
* RISC-V: Add misa runtime write supportMichael Clark2019-02-121-1/+3
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-121-11/+10Star
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-121-3/+3
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-091-2/+4
* RISC-V: Implement modular CSR helper interfaceMichael Clark2019-01-081-3/+32
* RISC-V: Allow setting and clearing multiple irqsMichael Clark2018-10-171-9/+13
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