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path: root/target/riscv/cpu.h
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* dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-061-2/+2
* target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-271-1/+5
* target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-271-1/+1
* target/riscv: Set the CPU resetvec directlyAlistair Francis2022-09-261-2/+1Star
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-071-0/+25
* target/riscv: Add vstimecmp supportAtish Patra2022-09-071-0/+4
* target/riscv: Add stimecmp supportAtish Patra2022-09-071-0/+5
* hw/intc: Move mtimer/mtimecmp to aclintAtish Patra2022-09-071-2/+0Star
* target/riscv: Use official extension names for AIA CSRsAnup Patel2022-09-071-2/+2
* target/riscv: Add Zihintpause supportDao Lu2022-09-071-0/+1
* target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen2022-09-071-0/+2
* target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel2022-09-071-0/+5
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-031-7/+16
* target/riscv: Add support for hpmcounters/hpmeventsAtish Patra2022-07-031-0/+11
* target/riscv: Implement mcountinhibit CSRAtish Patra2022-07-031-0/+2
* target/riscv: pmu: Make number of counters configurableAtish Patra2022-07-031-1/+1
* target/riscv: pmu: Rename the counters extension to pmuAtish Patra2022-07-031-1/+1
* target/riscv: rvv: Add tail agnostic for vv instructionseopXD2022-06-101-0/+2
* target/riscv: Wake on VS-level external interruptsAndrew Bresticker2022-06-101-0/+1
* target/riscv: add support for zmmul extension v0.1Weiwei Li2022-06-101-0/+1
* target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel2022-05-241-1/+7
* target/riscv: Fix typo of mimpid cpu optionFrank Chang2022-05-241-1/+1
* target/riscv: Add short-isa-string optionTsukasa OI2022-05-241-0/+2
* target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li2022-04-291-0/+13
* target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang2022-04-291-0/+4
* target/riscv: cpu: Add a config option for native debugBin Meng2022-04-221-1/+3
* hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-221-4/+4
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-221-0/+5
* target/riscv: Allow software access to MIP SEIPAlistair Francis2022-04-221-0/+8
* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-221-0/+5
* target/riscv: Introduce privilege version field in the CSR ops.Atish Patra2022-04-221-0/+2
* target/riscv: Add the privileged spec version 1.12.0Atish Patra2022-04-221-0/+1
* target/riscv: Define simpler privileged spec version numberingAtish Patra2022-04-221-2/+5
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-5/+5
* Move CPU softfloat unions to cpu-float.hMarc-André Lureau2022-04-061-1/+1
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-3/+1Star
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-3/+2Star
* target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li2022-03-031-0/+4
* target/riscv: add support for svinval extensionWeiwei Li2022-02-161-0/+1
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-161-0/+15
* target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel2022-02-161-0/+1
* target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel2022-02-161-0/+7
* target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel2022-02-161-0/+2
* target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel2022-02-161-7/+7
* target/riscv: Implement AIA local interrupt prioritiesAnup Patel2022-02-161-0/+12
* target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2022-02-161-0/+23
* target/riscv: Add AIA cpu featureAnup Patel2022-02-161-1/+2
* target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel2022-02-161-0/+5
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-161-0/+5
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