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path: root/target/riscv/cpu.h
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* target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark2019-06-241-0/+2
* target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis2019-06-241-0/+11
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-3/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+1
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-2/+0Star
* target/riscv: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-1/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-17/+4Star
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-241-0/+2
* target/riscv: Create settable CPU propertiesAlistair Francis2019-05-241-0/+8
* target/riscv: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
* RISC-V: linux-user support for RVE ABIKito Cheng2019-03-191-0/+4
* RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-191-0/+2
* RISC-V: Add hooks to use the gdb xml files.Jim Wilson2019-03-191-0/+2
* RISC-V: Add debug support for accessing CSRs.Jim Wilson2019-03-191-0/+5
* RISC-V: Add misa runtime write supportMichael Clark2019-02-121-1/+3
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-121-11/+10Star
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-121-3/+3
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-091-2/+4
* RISC-V: Implement modular CSR helper interfaceMichael Clark2019-01-081-3/+32
* RISC-V: Allow setting and clearing multiple irqsMichael Clark2018-10-171-9/+13
* riscv: remove define cpu_init()Igor Mammedov2018-09-051-1/+0Star
* RISC-V: Update address bits to support sv39 and sv48Michael Clark2018-09-041-4/+4
* RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark2018-05-061-4/+2Star
* RISC-V: Update E and I extension orderMichael Clark2018-05-061-0/+1
* RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark2018-05-061-1/+0Star
* cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
* RISC-V CPU Core DefinitionMichael Clark2018-03-061-0/+296
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