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path: root/target/riscv/cpu_helper.c
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* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-0/+5
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-2/+2
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+17
* target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
* target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
* target/riscv: Implement second stage MMUAlistair Francis2020-02-271-19/+174
* target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
* target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
* target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
* target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
* target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+61
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+18
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+18
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-2/+5
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-141-30/+18Star
* linux-user/riscv: Propagate fault addressGiuseppe Musacchio2019-10-281-1/+4
* RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt2019-10-281-4/+7
* RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt2019-10-281-3/+9
* riscv: rv32: Root page table address can be larger than 32-bitBin Meng2019-09-171-5/+5
* target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-171-0/+10
* RISC-V: Clear load reservations on context switch and SCJoel Sing2019-06-261-0/+10
* RISC-V: Fix a PMP check with the correct access sizeHesham Almatary2019-06-241-2/+1Star
* RISC-V: Check PMP during Page Table WalksHesham Almatary2019-06-241-1/+9
* RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary2019-06-241-1/+9
* RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary2019-06-241-3/+6
* RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary2019-06-241-0/+1
* target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark2019-06-241-0/+16
* target/riscv: Use env_cpu, env_archcpuRichard Henderson2019-06-101-6/+4Star
* target/riscv: Improve the scause logicAlistair Francis2019-05-241-1/+1
* target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-241-6/+27
* tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
* target/riscv: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-25/+21Star
* RISC-V: Update load reservation comment in do_interruptMichael Clark2019-03-191-1/+7
* RISC-V: Convert trap debugging to trace eventsMichael Clark2019-03-191-9/+3Star
* RISC-V: Add support for vectored interruptsMichael Clark2019-03-191-91/+54Star
* RISC-V: Change local interrupts from edge to levelMichael Clark2019-03-191-2/+2
* RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-191-0/+11
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-121-5/+5
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-091-1/+2
* RISC-V: Implement modular CSR helper interfaceMichael Clark2019-01-081-2/+2
* RISC-V: Add hartid and \n to interrupt loggingMichael Clark2018-12-201-8/+10
* RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark2018-10-171-0/+560
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