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path: root/target/riscv/cpu_helper.c
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* target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell2022-09-131-6/+3Star
* target/riscv: Add few cache related PMU eventsAtish Patra2022-09-071-0/+25
* target/riscv: Add vstimecmp supportAtish Patra2022-09-071-3/+8
* target/riscv: Use official extension names for AIA CSRsAnup Patel2022-09-071-1/+2
* target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen2022-09-071-0/+2
* target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel2022-09-071-6/+246
* target/riscv: Update default priority table for local interruptsAnup Patel2022-07-031-69/+65Star
* semihosting: Return void from do_common_semihostingRichard Henderson2022-06-281-1/+1
* target/riscv: rvv: Add tail agnostic for vv instructionseopXD2022-06-101-0/+2
* target/riscv: Wake on VS-level external interruptsAndrew Bresticker2022-06-101-1/+1
* target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel2022-05-241-0/+1
* target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel2022-05-241-2/+1Star
* hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-221-2/+2
* target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson2022-04-221-3/+3
* target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li2022-03-031-1/+5
* target/riscv: add support for svpbmt extensionWeiwei Li2022-02-161-1/+3
* target/riscv: add support for svnapot extensionWeiwei Li2022-02-161-3/+15
* target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li2022-02-161-0/+3
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-161-1/+12
* target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel2022-02-161-5/+5
* target/riscv: Implement AIA local interrupt prioritiesAnup Patel2022-02-161-21/+260
* target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2022-02-161-0/+14
* target/riscv: Improve delivery of guest external interruptsAnup Patel2022-02-161-0/+13
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-161-3/+34
* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-2/+1Star
* target/riscv: Split pm_enabled into mask and baseLIU Zhiwei2022-01-211-18/+6Star
* target/riscv: Create current pm fields in envLIU Zhiwei2022-01-211-0/+43
* target/riscv: Ignore the pc bits above XLENLIU Zhiwei2022-01-211-1/+1
* target/riscv: Create xl field in envLIU Zhiwei2022-01-211-32/+2Star
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-211-1/+1
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-211-1/+4
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-081-0/+3
* target/riscv: Fixup setting GVAAlistair Francis2022-01-081-15/+6Star
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-201-3/+13
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-0/+3
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-1/+19
* target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-20/+1Star
* target/riscv: remove force HS exceptionJose Martins2021-10-291-25/+1Star
* target/riscv: fix VS interrupts forwarding to HSJose Martins2021-10-291-20/+8Star
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-0/+18
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-221-2/+1Star
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+33
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-6/+6
* target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-211-0/+46
* target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-5/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-111-8/+24
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-111-9/+15
* target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
* riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
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