bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/riscv: Use env_cpu, env_archcpu	Richard Henderson	2019-06-10	1	-6/+6
*	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens	2019-05-24	1	-1/+3
*	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens	2019-05-24	1	-2/+5
*	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis	2019-05-24	1	-9/+8
*	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis	2019-05-24	1	-2/+0
*	RISC-V: Add support for vectored interrupts	Michael Clark	2019-03-19	1	-6/+6
*	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark	2019-03-19	1	-8/+2
*	RISC-V: Add debug support for accessing CSRs.	Jim Wilson	2019-03-19	1	-7/+25
*	target/riscv: fix counter-enable checks in ctr()	Xi Wang	2019-02-12	1	-3/+9
*	RISC-V: Add misa runtime write support	Michael Clark	2019-02-12	1	-1/+53
*	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark	2019-02-12	1	-4/+4
*	RISC-V: Implement mstatus.TSR/TW/TVM	Michael Clark	2019-02-12	1	-4/+13
*	RISC-V: Mark mstatus.fs dirty	Richard Henderson	2019-02-12	1	-12/+0
*	RISC-V: Implement existential predicates for CSRs	Michael Clark	2019-01-09	1	-76/+93
*	RISC-V: Implement atomic mip/sip CSR updates	Michael Clark	2019-01-09	1	-28/+28
*	RISC-V: Implement modular CSR helper interface	Michael Clark	2019-01-08	1	-0/+846