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path: root/target/riscv/csr.c
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* target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-161-84/+248
* target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-161-9/+1Star
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-181-85/+91
* target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang2020-11-031-1/+1
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-8/+10
* icount: rename functions to be consistent with the module nameClaudio Fontana2020-10-051-2/+2
* cpu-timers, icount: new modulesClaudio Fontana2020-10-051-2/+2
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-2/+2
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-1/+63
* target/riscv: Return the exception from invalid CSR accessesAlistair Francis2020-08-251-23/+23
* target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2020-08-251-0/+40
* target/riscv: Only support little endian guestsAlistair Francis2020-08-251-0/+5
* target/riscv: Only support a single VSXL lengthAlistair Francis2020-08-251-0/+9
* target/riscv: Convert MSTATUS MTL to GVAAlistair Francis2020-08-251-3/+3
* target/riscv: Don't allow guest to write to htinstAlistair Francis2020-08-251-1/+0Star
* target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li2020-07-221-1/+1
* target/riscv: support vector extension csrLIU Zhiwei2020-07-021-1/+74
* target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-113/+25Star
* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-4/+82
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+25
* target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis2020-02-271-1/+12
* target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis2020-02-271-4/+20
* target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
* target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
* target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis2020-02-271-0/+116
* target/riscv: Add Hypervisor CSR access functionsAlistair Francis2020-02-271-2/+134
* target/riscv: Fix CSR perm checking for HS modeAlistair Francis2020-02-271-4/+14
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-2/+5
* target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung2020-01-161-2/+1Star
* target/riscv: Remove atomic accesses to MIP CSRAlistair Francis2019-11-141-1/+1
* riscv: Skip checking CSR privilege level in debugger modeBin Meng2019-10-281-1/+4
* target/riscv: Fix mstatus dirty maskAlistair Francis2019-09-171-1/+1
* target/riscv: Create function to test if FP is enabledAlistair Francis2019-09-171-9/+11
* RISC-V: Add support for the Zicsr extensionPalmer Dabbelt2019-06-261-0/+6
* target/riscv: Add support for disabling/enabling CountersAlistair Francis2019-06-251-5/+12
* target/riscv: Add the mcountinhibit CSRAlistair Francis2019-06-251-2/+15
* target/riscv: Use env_cpu, env_archcpuRichard Henderson2019-06-101-6/+6
* target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens2019-05-241-1/+3
* target/riscv: More accurate handling of `sip` CSRJonathan Behrens2019-05-241-2/+5
* target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis2019-05-241-9/+8Star
* target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2019-05-241-2/+0Star
* RISC-V: Add support for vectored interruptsMichael Clark2019-03-191-6/+6
* RISC-V: Allow interrupt controllers to claim interruptsMichael Clark2019-03-191-8/+2Star
* RISC-V: Add debug support for accessing CSRs.Jim Wilson2019-03-191-7/+25
* target/riscv: fix counter-enable checks in ctr()Xi Wang2019-02-121-3/+9
* RISC-V: Add misa runtime write supportMichael Clark2019-02-121-1/+53
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-121-4/+4
* RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2019-02-121-4/+13
* RISC-V: Mark mstatus.fs dirtyRichard Henderson2019-02-121-12/+0Star
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-091-76/+93
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