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path: root/target/riscv/fpu_helper.c
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* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-031-44/+45
* target/riscv: add support for zfinxWeiwei Li2022-03-031-44/+45
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-201-0/+5
* target/riscv: introduce floating-point rounding mode enumFrank Chang2021-12-201-6/+6
* target/riscv: zfh: half-precision floating-point classifyKito Cheng2021-12-201-0/+6
* target/riscv: zfh: half-precision floating-point compareKito Cheng2021-12-201-0/+21
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+67
* target/riscv: zfh: half-precision computationalKito Cheng2021-12-201-0/+86
* target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao2021-10-291-4/+12
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-8/+8
* target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2020-12-181-8/+0Star
* target/riscv: Check nanboxed inputs to fp helpersRichard Henderson2020-08-221-18/+46
* target/riscv: Generate nanboxed results from fp helpersRichard Henderson2020-08-221-19/+23
* target/riscv: vector floating-point classify instructionsLIU Zhiwei2020-07-021-30/+3Star
* target/riscv: rationalise softfloat includesAlex Bennée2019-08-191-0/+1
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-121-3/+3
* Clean up includesMarkus Armbruster2018-12-201-1/+0Star
* target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-4/+2Star
* RISC-V FPU SupportMichael Clark2018-03-061-0/+373
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