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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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path:
root
/
target
/
riscv
/
helper.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
2021-05-11
1
-10
/
+8
*
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
2020-12-18
1
-16
/
+8
*
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
2020-11-10
1
-1
/
+2
*
target/riscv: Remove the hyp load and store functions
Alistair Francis
2020-11-10
1
-2
/
+0
*
target/riscv: Support the Virtual Instruction fault
Alistair Francis
2020-08-25
1
-0
/
+1
*
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
2020-08-25
1
-0
/
+3
*
target/riscv: vector compress instruction
LIU Zhiwei
2020-07-02
1
-0
/
+5
*
target/riscv: vector register gather instruction
LIU Zhiwei
2020-07-02
1
-0
/
+9
*
target/riscv: vector slide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector element index instruction
LIU Zhiwei
2020-07-02
1
-0
/
+5
*
target/riscv: vector iota instruction
LIU Zhiwei
2020-07-02
1
-0
/
+5
*
target/riscv: set-X-first mask bit
LIU Zhiwei
2020-07-02
1
-0
/
+4
*
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
2020-07-02
1
-0
/
+2
*
target/riscv: vector mask population count vmpopc
LIU Zhiwei
2020-07-02
1
-0
/
+2
*
target/riscv: vector mask-register logical instructions
LIU Zhiwei
2020-07-02
1
-0
/
+9
*
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+3
*
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+10
*
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+7
*
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+11
*
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+11
*
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: vector floating-point merge instructions
LIU Zhiwei
2020-07-02
1
-0
/
+4
*
target/riscv: vector floating-point classify instructions
LIU Zhiwei
2020-07-02
1
-0
/
+4
*
target/riscv: vector floating-point compare instructions
LIU Zhiwei
2020-07-02
1
-0
/
+37
*
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
2020-07-02
1
-0
/
+19
*
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
2020-07-02
1
-0
/
+4
*
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+49
*
target/riscv: vector widening floating-point multiply
LIU Zhiwei
2020-07-02
1
-0
/
+5
*
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+16
*
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
1
-0
/
+16
*
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
2020-07-02
1
-0
/
+22
*
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
2020-07-02
1
-0
/
+9
*
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector integer merge and move instructions
LIU Zhiwei
2020-07-02
1
-0
/
+17
*
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+22
*
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
2020-07-02
1
-0
/
+19
*
target/riscv: vector integer divide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector integer min/max instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector integer comparison instructions
LIU Zhiwei
2020-07-02
1
-0
/
+57
*
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+25
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