Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | target/riscv: Add checks for several RVC reserved operands | Richard Henderson | 2019-05-24 | 1 | -1/+6 |
* | target/riscv: Split RVC32 and RVC64 insns into separate files | Richard Henderson | 2019-05-24 | 1 | -32/+3 |
* | target/riscv: Use pattern groups in insn16.decode | Richard Henderson | 2019-05-24 | 1 | -6/+23 |
* | target/riscv: Merge argument decode for RVC shifti | Richard Henderson | 2019-05-24 | 1 | -6/+6 |
* | target/riscv: Merge argument sets for insn32 and insn16 | Richard Henderson | 2019-05-24 | 1 | -37/+47 |
* | target/riscv: Convert quadrant 2 of RVXC insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+31 |
* | target/riscv: Convert quadrant 1 of RVXC insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+43 |
* | target/riscv: Convert quadrant 0 of RVXC insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+55 |