Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | target/riscv: Allow generating hlv/hlvx/hsv instructions | Alistair Francis | 2020-08-25 | 1 | -0/+5 |
* | target/riscv: add vector amo operations | LIU Zhiwei | 2020-07-02 | 1 | -0/+11 |
* | target/riscv: Convert RV64D insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+8 |
* | target/riscv: Convert RV64F insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+6 |
* | target/riscv: Convert RV64A insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+13 |
* | target/riscv: Convert RVXM insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+7 |
* | target/riscv: Convert RVXI arithmetic insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+13 |
* | target/riscv: Convert RV64I load/store insns to decodetree | Bastian Koppelmann | 2019-03-13 | 1 | -0/+25 |