summaryrefslogtreecommitdiffstats
path: root/target/riscv/insn32.decode
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson2019-05-241-3/+7
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-131-1/+2
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-131-1/+2
* target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-131-0/+15
* target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-131-0/+28
* target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-131-0/+35
* target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-131-0/+17
* target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-131-0/+10
* target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-131-0/+8
* target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-131-0/+2
* target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-131-0/+25
* target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-131-0/+10
* target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-131-0/+19
* target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-131-0/+30
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 04:33:47 +0100