summaryrefslogtreecommitdiffstats
path: root/target/riscv/insn_trans/trans_rvh.c.inc
Commit message (Expand)AuthorAgeFilesLines
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-2/+2
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-011-210/+56Star
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-26/+26
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-2/+6
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-101-14/+6Star
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-78/+45Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-1/+1
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+340
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+37