Commit message (Expand) | Author | Age | Files | Lines | |
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* | exec/memop: Adding signedness to quad definitions | Frédéric Pétrot | 2022-01-08 | 1 | -2/+2 |
* | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson | 2021-09-01 | 1 | -210/+56![]() |
* | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr | Richard Henderson | 2021-09-01 | 1 | -26/+26 |
* | target/riscv: Consolidate RV32/64 32-bit instructions | Alistair Francis | 2021-05-11 | 1 | -2/+6 |
* | target/riscv: Split the Hypervisor execute load helpers | Alistair Francis | 2020-11-10 | 1 | -14/+6![]() |
* | target/riscv: Remove the hyp load and store functions | Alistair Francis | 2020-11-10 | 1 | -78/+45![]() |
* | target/riscv: Support the Virtual Instruction fault | Alistair Francis | 2020-08-25 | 1 | -1/+1 |
* | target/riscv: Allow generating hlv/hlvx/hsv instructions | Alistair Francis | 2020-08-25 | 1 | -0/+340 |
* | meson: rename included C source files to .c.inc | Paolo Bonzini | 2020-08-21 | 1 | -0/+37 |