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path: root/target/riscv/insn_trans/trans_rvi.inc.c
Commit message (Expand)AuthorAgeFilesLines
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-2/+2
* icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-1/+0Star
* RISC-V: Add support for the Zifencei extensionPalmer Dabbelt2019-06-261-0/+4
* target/riscv: Split gen_arith_imm into functional and tempRichard Henderson2019-05-241-7/+7
* target/riscv: Use pattern groups in insn16.decodeRichard Henderson2019-05-241-0/+6
* RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau2019-05-241-3/+3
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-131-9/+9
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-131-30/+63
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-131-14/+7Star
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-131-19/+79
* target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-131-8/+19
* target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-131-14/+21
* target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-131-13/+33
* target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-131-1/+27
* target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-131-0/+79
* target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-131-0/+19
* target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-131-0/+168
* target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-131-0/+20
* target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-131-0/+48
* target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-131-0/+49
* target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-131-0/+35
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