bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/riscv: Split the Hypervisor execute load helpers	Alistair Francis	2020-11-10	1	-27/+9
*	target/riscv: Remove the hyp load and store functions	Alistair Francis	2020-11-10	1	-86/+0
*	target/riscv: Remove the HS_TWO_STAGE flag	Alistair Francis	2020-11-10	1	-12/+0
*	target/riscv: Set the virtualised MMU mode when doing hyp accesses	Alistair Francis	2020-11-10	1	-13/+17
*	target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit	Yifei Jiang	2020-11-03	1	-7/+4
*	target/riscv: Fix implementation of HLVX.WU instruction	Georg Kotheimer	2020-10-22	1	-3/+3
*	riscv: Convert interrupt logs to use qemu_log_mask()	Alistair Francis	2020-10-22	1	-1/+0
*	target/riscv: Support the Virtual Instruction fault	Alistair Francis	2020-08-25	1	-4/+38
*	target/riscv: Return the exception from invalid CSR accesses	Alistair Francis	2020-08-25	1	-6/+12
*	target/riscv: Update the Hypervisor trap return/entry	Alistair Francis	2020-08-25	1	-6/+2
*	target/riscv: Allow generating hlv/hlvx/hsv instructions	Alistair Francis	2020-08-25	1	-0/+114
*	target/riscv: Implement checks for hfence	Alistair Francis	2020-06-19	1	-0/+13
*	target/riscv: Drop support for ISA spec version 1.09.1	Alistair Francis	2020-06-03	1	-12/+5
*	target/riscv: Correctly implement TSR trap	Alistair Francis	2020-03-17	1	-1/+1
*	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	Alistair Francis	2020-02-27	1	-1/+1
*	target/riscv: Add support for the 32-bit MSTATUSH CSR	Alistair Francis	2020-02-27	1	-0/+4
*	target/riscv: Add Hypervisor trap return support	Alistair Francis	2020-02-27	1	-10/+52
*	target/riscv: Generate illegal instruction on WFI when V=1	Alistair Francis	2020-02-27	1	-2/+3
*	riscv: Set xPIE to 1 after xRET	Yiting Wang	2020-01-16	1	-2/+2
*	target/riscv: Use env_cpu, env_archcpu	Richard Henderson	2019-06-10	1	-4/+3
*	target/riscv: Do not allow sfence.vma from user mode	Jonathan Behrens	2019-05-24	1	-3/+4
*	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark	2019-02-12	1	-14/+14
*	RISC-V: Implement mstatus.TSR/TW/TVM	Michael Clark	2019-02-12	1	-4/+21
*	RISC-V: Implement modular CSR helper interface	Michael Clark	2019-01-08	1	-598/+15
*	RISC-V: Update CSR and interrupt definitions	Michael Clark	2018-10-17	1	-1/+1
*	RISC-V: Move non-ops from op_helper to cpu_helper	Michael Clark	2018-10-17	1	-34/+0
*	RISC-V: Allow setting and clearing multiple irqs	Michael Clark	2018-10-17	1	-9/+15
*	RISC-V: Add trailing '\n' to qemu_log() calls	Philippe Mathieu-Daudé	2018-06-08	1	-2/+4
*	RISC-V: No traps on writes to misa,minstret,mcycle	Michael Clark	2018-05-06	1	-12/+13
*	RISC-V: Make mtvec/stvec ignore vectored traps	Michael Clark	2018-05-06	1	-6/+8
*	RISC-V: Add mcycle/minstret support for -icount auto	Michael Clark	2018-05-06	1	-2/+26
*	RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10	Michael Clark	2018-05-06	1	-14/+48
*	RISC-V: Allow S-mode mxr access when priv ISA >= v1.10	Michael Clark	2018-05-06	1	-2/+5
*	RISC-V: Hardwire satp to 0 for no-mmu case	Michael Clark	2018-05-06	1	-2/+5
*	RISC-V: Workaround for critical mstatus.FS bug	Michael Clark	2018-03-29	1	-2/+15
*	RISC-V CPU Helpers	Michael Clark	2018-03-06	1	-0/+669