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path: root/target/riscv/pmp.c
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* target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-161-2/+2
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-031-11/+18
* target/riscv: Change the TLB page size depends on PMP entries.Zong Li2020-08-221-0/+52
* riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying2020-08-221-3/+2Star
* target/riscv: Fix pmp NA4 implementationAlexandre Mergnat2020-07-141-1/+1
* target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis2020-06-191-5/+9
* target/riscv: PMP violation due to wrong size parameterDayeol Lee2019-10-281-1/+12
* target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2019-09-171-21/+10Star
* target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2019-09-171-4/+0Star
* RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary2019-06-241-4/+5
* RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary2019-06-241-3/+3
* target/riscv: Fix PMP range boundary address bugDayeol Lee2019-06-241-1/+1
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* riscv: pmp: Log pmp access errors as guest errorsAlistair Francis2019-03-191-7/+13
* target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel2018-12-201-1/+1
* target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee2018-10-301-1/+1
* RISC-V Physical Memory ProtectionMichael Clark2018-03-061-0/+380