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path: root/target/riscv/translate.c
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* RISC-V: Add priv_ver to DisasContextAlistair Francis2019-02-121-2/+5
* RISC-V: Mark mstatus.fs dirtyRichard Henderson2019-02-121-1/+39
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-121-5/+5
* RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt2018-11-141-2/+0Star
* target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann2018-11-141-5/+13
* target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann2018-11-141-1/+3
* target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota2018-09-051-6/+1Star
* target/riscv: optimize indirect branchesEmilio G. Cota2018-09-051-1/+1
* target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota2018-09-051-1/+1
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-10/+10
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-111-49/+17Star
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| * target/riscv: Use new atomic min/max expandersRichard Henderson2018-05-101-49/+17Star
* | target/riscv: convert to TranslatorOpsEmilio G. Cota2018-05-091-78/+80
* | target/riscv: convert to DisasContextBaseEmilio G. Cota2018-05-091-65/+64Star
* | target/riscv: convert to DisasJumpTypeEmilio G. Cota2018-05-091-44/+28Star
* | target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-3/+3
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* RISC-V: Add mcycle/minstret support for -icount autoMichael Clark2018-05-061-0/+2
* RISC-V: Remove erroneous comment from translate.cMichael Clark2018-05-061-1/+0Star
* RISC-V TCG Code GenerationMichael Clark2018-03-061-0/+1978
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