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path: root/target/riscv/vector_helper.c
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* target/riscv: Fix vill field write in vtypeLIU Zhiwei2022-02-161-0/+1
* target/riscv: Adjust vector address with maskLIU Zhiwei2022-01-211-10/+15
* target/riscv: Fix check range for first fault onlyLIU Zhiwei2022-01-211-2/+2
* target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2022-01-211-2/+5
* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-1/+2
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-201-0/+21
* target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang2021-12-201-18/+18
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-201-0/+191
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-201-0/+183
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-74/+136
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-201-20/+25
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-201-1/+6
* target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-201-7/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-201-205/+0Star
* target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2021-12-201-6/+6
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-201-26/+26
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-201-45/+96
* target/riscv: rvv-1.0: slide instructionsFrank Chang2021-12-201-7/+12
* target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2021-12-201-4/+0Star
* target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang2021-12-201-9/+0Star
* target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2021-12-201-9/+0Star
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang2021-12-201-15/+6Star
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-201-0/+74
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-201-0/+31
* target/riscv: rvv-1.0: register gather instructionsFrank Chang2021-12-201-9/+14
* target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang2021-12-201-4/+0Star
* target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: count population in mask instructionFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang2021-12-201-44/+55
* target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang2021-12-201-0/+65
* target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang2021-12-201-55/+19Star
* target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang2021-12-201-4/+4
* target/riscv: rvv-1.0: index load and store instructionsFrank Chang2021-12-201-56/+42Star
* target/riscv: rvv-1.0: stride load and store instructionsFrank Chang2021-12-201-130/+69Star
* target/riscv: rvv-1.0: configure instructionsFrank Chang2021-12-201-1/+13
* target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang2021-12-201-125/+0Star
* target/riscv: rvv-1.0: add VMA and VTAFrank Chang2021-12-201-1038/+889Star
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang2021-12-201-147/+105Star
* target/riscv: Use FIELD_EX32() to extract wd fieldFrank Chang2021-12-201-1/+1
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-4/+0Star
* target/riscv: fix vrgather macro index variable type bugFrank Chang2021-05-111-2/+4
* target/riscv: Fixup saturate subtract functionLIU Zhiwei2021-05-111-4/+4
* softfloat: Implement the full set of comparisons for float16Kito Cheng2020-08-281-25/+0Star
* target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth2020-08-051-2/+2
* target/riscv: vector compress instructionLIU Zhiwei2020-07-021-0/+26
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