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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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path:
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target
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riscv
/
vector_helper.c
Commit message (
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Author
Age
Files
Lines
*
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
2021-05-11
1
-4
/
+0
*
target/riscv: fix vrgather macro index variable type bug
Frank Chang
2021-05-11
1
-2
/
+4
*
target/riscv: Fixup saturate subtract function
LIU Zhiwei
2021-05-11
1
-4
/
+4
*
softfloat: Implement the full set of comparisons for float16
Kito Cheng
2020-08-28
1
-25
/
+0
*
target/riscv/vector_helper: Fix build on 32-bit big endian hosts
Thomas Huth
2020-08-05
1
-2
/
+2
*
target/riscv: vector compress instruction
LIU Zhiwei
2020-07-02
1
-0
/
+26
*
target/riscv: vector register gather instruction
LIU Zhiwei
2020-07-02
1
-0
/
+60
*
target/riscv: vector slide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+114
*
target/riscv: vector element index instruction
LIU Zhiwei
2020-07-02
1
-0
/
+24
*
target/riscv: vector iota instruction
LIU Zhiwei
2020-07-02
1
-0
/
+29
*
target/riscv: set-X-first mask bit
LIU Zhiwei
2020-07-02
1
-0
/
+63
*
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
2020-07-02
1
-0
/
+19
*
target/riscv: vector mask population count vmpopc
LIU Zhiwei
2020-07-02
1
-0
/
+20
*
target/riscv: vector mask-register logical instructions
LIU Zhiwei
2020-07-02
1
-0
/
+40
*
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+46
*
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+39
*
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+11
*
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
2020-07-02
1
-0
/
+74
*
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+39
*
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+42
*
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
1
-0
/
+33
*
target/riscv: vector floating-point merge instructions
LIU Zhiwei
2020-07-02
1
-0
/
+24
*
target/riscv: vector floating-point classify instructions
LIU Zhiwei
2020-07-02
1
-0
/
+91
*
target/riscv: vector floating-point compare instructions
LIU Zhiwei
2020-07-02
1
-0
/
+174
*
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
2020-07-02
1
-0
/
+85
*
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
2020-07-02
1
-0
/
+27
*
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
2020-07-02
1
-0
/
+43
*
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+91
*
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+251
*
target/riscv: vector widening floating-point multiply
LIU Zhiwei
2020-07-02
1
-0
/
+22
*
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+49
*
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
1
-0
/
+83
*
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
1
-0
/
+111
*
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
2020-07-02
1
-0
/
+141
*
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+117
*
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
2020-07-02
1
-0
/
+205
*
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
2020-07-02
1
-0
/
+107
*
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+100
*
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+385
*
target/riscv: vector integer merge and move instructions
LIU Zhiwei
2020-07-02
1
-0
/
+88
*
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+45
*
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
2020-07-02
1
-0
/
+88
*
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
2020-07-02
1
-0
/
+51
*
target/riscv: vector integer divide instructions
LIU Zhiwei
2020-07-02
1
-0
/
+74
*
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
2020-07-02
1
-0
/
+163
*
target/riscv: vector integer min/max instructions
LIU Zhiwei
2020-07-02
1
-0
/
+71
*
target/riscv: vector integer comparison instructions
LIU Zhiwei
2020-07-02
1
-0
/
+123
*
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+14
*
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
2020-07-02
1
-0
/
+79
*
target/riscv: vector bitwise logical instructions
LIU Zhiwei
2020-07-02
1
-0
/
+51
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