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* target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson2021-10-221-44/+45
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-223-52/+97
* target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-222-17/+32
* target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson2021-10-221-1/+6
* target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-222-3/+39
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-214-43/+62
* target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson2021-10-211-14/+17
* target/riscv: Properly check SEW in amo_opRichard Henderson2021-10-211-12/+14
* target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson2021-10-211-1/+2
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-215-1/+47
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-216-32/+43
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-216-67/+98
* target/riscv: Create RISCVMXL enumerationRichard Henderson2021-10-211-3/+5
* target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-212-45/+48
* target/riscv: Organise the CPU propertiesAlistair Francis2021-10-211-7/+10
* target/riscv: Remove some unused macrosAlistair Francis2021-10-211-8/+0Star
* target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-212-8/+8
* target/riscv: Fix orc.b implementationPhilipp Tomsich2021-10-211-5/+8
* target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht2021-10-211-5/+5
* target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang2021-10-211-1/+2
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-164-34/+7Star
* target/riscv: Remove dead code after exceptionRichard Henderson2021-10-161-5/+1Star
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-072-13/+21
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-073-33/+0Star
* target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-072-77/+21Star
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-074-79/+15Star
* target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-074-55/+18Star
* target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-072-41/+50
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-074-1/+65
* target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-072-18/+24
* target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-072-78/+0Star
* target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-072-63/+0Star
* target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-072-13/+23
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-072-0/+8
* target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
* target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
* target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-1/+1
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-212-16/+16
* target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
* target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis2021-09-201-0/+30
* target/riscv: Fix satp writeLIU Zhiwei2021-09-201-1/+1
* target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-202-2/+3
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-7/+2Star
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-2/+3
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26Star
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57Star
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 17:50:23 +0100