summaryrefslogtreecommitdiffstats
path: root/target/riscv
Commit message (Expand)AuthorAgeFilesLines
...
* target/riscv: rvv-1.0: floating-point classify instructionsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: floating-point square-root instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-203-13/+42
* target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang2021-12-202-51/+80
* target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang2021-12-204-0/+176
* target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang2021-12-204-109/+38Star
* target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang2021-12-201-4/+4
* target/riscv: rvv-1.0: index load and store instructionsFrank Chang2021-12-204-151/+145Star
* target/riscv: rvv-1.0: stride load and store instructionsFrank Chang2021-12-204-447/+300Star
* target/riscv: rvv-1.0: configure instructionsFrank Chang2021-12-202-36/+40
* target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang2021-12-204-316/+0Star
* target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang2021-12-201-1/+34
* target/riscv: introduce more imm value modes in translator functionsFrank Chang2021-12-201-49/+66
* target/riscv: rvv-1.0: update check functionsFrank Chang2021-12-201-208/+507
* target/riscv: rvv-1.0: add VMA and VTAFrank Chang2021-12-202-1038/+891Star
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-203-16/+42
* target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang2021-12-204-187/+111Star
* target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang2021-12-201-0/+5
* target/riscv: rvv-1.0: add vlenb registerGreentime Hu2021-12-202-0/+8
* target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2021-12-202-0/+24
* target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang2021-12-201-13/+0Star
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-204-14/+109
* target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2021-12-202-1/+2
* target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-204-2/+33
* target/riscv: Use FIELD_EX32() to extract wd fieldFrank Chang2021-12-201-1/+1
* target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang2021-12-202-9/+9
* target/riscv: zfh: add Zfhmin cpu propertyFrank Chang2021-12-201-0/+1
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-203-8/+17
* target/riscv: zfh: add Zfh cpu propertyFrank Chang2021-12-201-0/+1
* target/riscv: zfh: half-precision floating-point classifyKito Cheng2021-12-204-0/+20
* target/riscv: zfh: half-precision floating-point compareKito Cheng2021-12-204-0/+64
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-205-0/+396
* target/riscv: zfh: half-precision computationalKito Cheng2021-12-205-0/+255
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-204-0/+78
* target/riscv: machine: Sort the .subsectionsBin Meng2021-11-171-46/+46
* target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-022-21/+2Star
* target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao2021-10-291-4/+12
* target/riscv: remove force HS exceptionJose Martins2021-10-293-33/+1Star
* target/riscv: fix VS interrupts forwarding to HSJose Martins2021-10-291-20/+8Star
* target/riscv: Allow experimental J-ext to be turned onAlexey Baturo2021-10-281-0/+4
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-283-2/+57
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-285-0/+17
* target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo2021-10-281-0/+7
* target/riscv: Add J extension state descriptionAlexey Baturo2021-10-281-0/+27
* target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-283-0/+298
* target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo2021-10-281-0/+96
* target/riscv: Add J-extension into RISC-VAlexey Baturo2021-10-281-0/+2
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-223-20/+25
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 05:07:00 +0100