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* target/riscv: vector single-width integer add and subtractLIU Zhiwei2020-07-024-0/+509
* target/riscv: add vector amo operationsLIU Zhiwei2020-07-026-0/+339
* target/riscv: add fault-only-first unit stride loadLIU Zhiwei2020-07-024-0/+212
* target/riscv: add vector index load and store instructionsLIU Zhiwei2020-07-024-0/+293
* target/riscv: add vector stride load and store instructionsLIU Zhiwei2020-07-026-0/+914
* target/riscv: add an internals.h headerLIU Zhiwei2020-07-021-0/+24
* target/riscv: add vector configure instructionLIU Zhiwei2020-07-027-12/+210
* target/riscv: support vector extension csrLIU Zhiwei2020-07-022-1/+89
* target/riscv: implementation-defined constant parametersLIU Zhiwei2020-07-022-0/+12
* target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei2020-07-022-1/+14
* hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2020-06-191-8/+8
* target/riscv: Rename IBEX CPU init routineBin Meng2020-06-191-2/+2
* target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis2020-06-191-5/+9
* target/riscv: Implement checks for hfenceAlistair Francis2020-06-193-26/+24Star
* target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis2020-06-194-41/+63
* target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis2020-06-191-2/+7
* target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis2020-06-191-1/+1
* riscv: Keep the CPU init routine names consistentBin Meng2020-06-191-4/+4
* riscv: Generalize CPU init routine for the imacu CPUBin Meng2020-06-191-21/+10Star
* riscv: Generalize CPU init routine for the gcsu CPUBin Meng2020-06-191-14/+6Star
* riscv: Generalize CPU init routine for the base CPUBin Meng2020-06-191-13/+5Star
* riscv: Add helper to make NaN-boxing for FP registerIan Jiang2020-06-191-2/+15
* Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell2020-06-081-2/+4
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| * target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé2020-06-051-2/+4
* | target/riscv: Add the lowRISC Ibex CPUAlistair Francis2020-06-032-0/+11
* | target/riscv: Don't set PMP feature in the cpu initAlistair Francis2020-06-031-5/+0Star
* | target/riscv: Disable the MMU correctlyAlistair Francis2020-06-031-2/+3
* | target/riscv: Don't overwrite the reset vectorAlistair Francis2020-06-031-1/+2
* | target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-037-200/+63Star
* | target/riscv: Remove the deprecated CPUsAlistair Francis2020-06-032-35/+0Star
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* target/riscv: Add a sifive-e34 cpu typeCorey Wharton2020-04-292-0/+11
* riscv: Fix Stage2 SV32 page table walkAnup Patel2020-04-291-6/+1Star
* riscv: AND stage-1 and stage-2 protection flagsAlistair Francis2020-04-291-3/+5
* riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis2020-04-291-1/+2
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-192-4/+5
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-182-4/+5
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-172-11/+11
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* target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal2020-03-171-1/+8
* target/riscv: Correctly implement TSR trapAlistair Francis2020-03-171-1/+1
* RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt2020-03-051-2/+2
* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-273-4/+92
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-272-0/+6
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-274-4/+15
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-276-0/+62
* target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
* target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
* target/riscv: Implement second stage MMUAlistair Francis2020-02-272-19/+175
* target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
* target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
* target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
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