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bwlp/qemu.git
block_qcow2_cluster_info
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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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path:
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riscv
Commit message (
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Author
Age
Files
Lines
...
*
target/riscv: configure and turn on vector extension from command line
LIU Zhiwei
2020-07-02
2
-1
/
+46
*
target/riscv: vector compress instruction
LIU Zhiwei
2020-07-02
4
-0
/
+64
*
target/riscv: vector register gather instruction
LIU Zhiwei
2020-07-02
4
-0
/
+150
*
target/riscv: vector slide instructions
LIU Zhiwei
2020-07-02
4
-0
/
+155
*
target/riscv: floating-point scalar move instructions
LIU Zhiwei
2020-07-02
2
-0
/
+52
*
target/riscv: integer scalar move instruction
LIU Zhiwei
2020-07-02
3
-0
/
+67
*
target/riscv: integer extract instruction
LIU Zhiwei
2020-07-02
2
-0
/
+117
*
target/riscv: vector element index instruction
LIU Zhiwei
2020-07-02
4
-0
/
+56
*
target/riscv: vector iota instruction
LIU Zhiwei
2020-07-02
4
-0
/
+62
*
target/riscv: set-X-first mask bit
LIU Zhiwei
2020-07-02
4
-0
/
+98
*
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
2020-07-02
4
-0
/
+54
*
target/riscv: vector mask population count vmpopc
LIU Zhiwei
2020-07-02
4
-0
/
+55
*
target/riscv: vector mask-register logical instructions
LIU Zhiwei
2020-07-02
4
-0
/
+92
*
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
2020-07-02
4
-0
/
+54
*
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
2020-07-02
4
-0
/
+58
*
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
2020-07-02
4
-0
/
+24
*
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
2020-07-02
4
-0
/
+133
*
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
4
-0
/
+103
*
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
4
-0
/
+106
*
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
4
-0
/
+56
*
target/riscv: vector floating-point merge instructions
LIU Zhiwei
2020-07-02
4
-0
/
+68
*
target/riscv: vector floating-point classify instructions
LIU Zhiwei
2020-07-02
6
-30
/
+107
*
target/riscv: vector floating-point compare instructions
LIU Zhiwei
2020-07-02
4
-0
/
+258
*
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
2020-07-02
4
-0
/
+118
*
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
2020-07-02
4
-0
/
+50
*
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
2020-07-02
4
-0
/
+93
*
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
4
-0
/
+126
*
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
4
-0
/
+334
*
target/riscv: vector widening floating-point multiply
LIU Zhiwei
2020-07-02
4
-0
/
+33
*
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
2020-07-02
4
-0
/
+77
*
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
4
-0
/
+257
*
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
4
-0
/
+250
*
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
2020-07-02
4
-0
/
+168
*
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
2020-07-02
4
-0
/
+148
*
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
2020-07-02
4
-0
/
+243
*
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
2020-07-02
4
-0
/
+122
*
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
2020-07-02
4
-0
/
+129
*
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
2020-07-02
4
-0
/
+444
*
target/riscv: vector integer merge and move instructions
LIU Zhiwei
2020-07-02
4
-0
/
+225
*
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
2020-07-02
4
-0
/
+83
*
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
2020-07-02
4
-0
/
+139
*
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
2020-07-02
4
-0
/
+84
*
target/riscv: vector integer divide instructions
LIU Zhiwei
2020-07-02
4
-0
/
+125
*
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
2020-07-02
4
-0
/
+214
*
target/riscv: vector integer min/max instructions
LIU Zhiwei
2020-07-02
4
-0
/
+122
*
target/riscv: vector integer comparison instructions
LIU Zhiwei
2020-07-02
4
-0
/
+246
*
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
2020-07-02
4
-0
/
+123
*
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
2020-07-02
4
-0
/
+165
*
target/riscv: vector bitwise logical instructions
LIU Zhiwei
2020-07-02
4
-0
/
+96
*
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
LIU Zhiwei
2020-07-02
4
-0
/
+294
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