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* target/rx: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-6/+0Star
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+3
| | | | | | | | | | | Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/rx: update PC correctly in wait instructionTomoaki Kawada2022-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | `cpu_pc` at this point does not necessary point to the current instruction (i.e., the wait instruction being translated), so it's incorrect to calculate the new value of `cpu_pc` based on this. It must be updated with `ctx->base.pc_next`, which contains the correct address of the next instruction. This change fixes the wait instruction skipping the subsequent branch when used in an idle loop like this: 0: wait bra.b 0b brk // should be unreachable Signed-off-by: Tomoaki Kawada <i@yvt.jp> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417060224.2131788-1-i@yvt.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/rx: Swap stack pointers on clrpsw/setpsw instructionRichard Henderson2022-04-211-1/+6
| | | | | | | | | | We properly perform this swap in helper_set_psw for MVTC, but we missed doing so for the CLRPSW/SETPSW of the U bit. Reported-by: Tomoaki Kawada <i@yvt.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20220417165130.695085-5-richard.henderson@linaro.org>
* target/rx: Move DISAS_UPDATE check for write to PSWRichard Henderson2022-04-211-10/+4Star
| | | | | | | | | Have one check in move_to_cr instead of one in each function that calls move_to_cr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20220417165130.695085-4-richard.henderson@linaro.org>
* target/rx: Store PSW.U in tb->flagsRichard Henderson2022-04-211-19/+23
| | | | | | | | | With this, we don't need movcond to determine which stack pointer is current. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20220417165130.695085-3-richard.henderson@linaro.org>
* target/rx: Put tb_flags into DisasContextRichard Henderson2022-04-211-1/+3
| | | | | | | | | Copy tb->flags into ctx->tb_flags; we'll want to modify this value throughout the tb in future. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20220417165130.695085-2-richard.henderson@linaro.org>
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
| | | | | | | | | | We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
* target/rx: Drop checks for singlestep_enabledRichard Henderson2021-10-161-10/+2Star
| | | | | | | GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-14/+0Star
| | | | | | | | | The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/rx: Use translator_use_goto_tbRichard Henderson2021-07-091-10/+1Star
| | | | | | | | Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
| | | | | | | | | | | | | | | | | | | | The root trace-events only declares a single TCG event: $ git grep -w tcg trace-events trace-events:115:# tcg/tcg-op.c trace-events:137:vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" and only a tcg/tcg-op.c uses it: $ git grep -l trace_guest_mem_before_tcg tcg/tcg-op.c therefore it is pointless to include "trace-tcg.h" in each target (because it is not used). Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210629050935.2570721-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/rx: Fix some comment spelling errorsLichang Zhao2020-10-271-1/+1
| | | | | | | | | | | There are many spelling errors in the comments of target/rx. Use spellcheck to check the spelling errors, then fix them. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daude<f4bug@amsat.org> Message-Id: <20201009064449.2336-5-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* rx: Rename QOM type check macrosEduardo Habkost2020-09-021-1/+1
| | | | | | | | | | | | | | | | | | Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the function name would conflict with the typedef name. Rename the RXCPU* QOM type check macros to RX_CPU*, so we will avoid the conflict and make the macro names consistent with the TYPE_RX_CPU constant name. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-53-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* meson: targetPaolo Bonzini2020-08-211-1/+1
| | | | | | | | | Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/rx/translate: Add missing fall through commentPhilippe Mathieu-Daudé2020-04-081-0/+1
| | | | | | | | | | | Coverity reported a missing fall through comment, add it. Fixes: e5918d7d7f0 ("target/rx: TCG translation") Reported-by: Coverity (CID 1422222 MISSING_BREAK) Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200403184419.28556-1-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/rx: CPU definitionsYoshinori Sato2020-03-191-5/+12
| | | | | | | | | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to extable array, use rx_cpu_tlb_fill() extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset after qemu_init_vcpu, make rx_crname a function] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp> Acked-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use GByteArray in gdbstub (rebase commit a010bdbe), use device_class_set_parent_reset (rebase commit 781c67ca)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* target/rx: TCG translationYoshinori Sato2020-03-191-0/+2432
This part only supported RXv1 instructions. Instruction manual: https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-5-ysato@users.sourceforge.jp> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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