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* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently search both the root and the tcg/ directories for tcg files: $ git grep '#include "tcg/' | wc -l 28 $ git grep '#include "tcg[^/]' | wc -l 94 To simplify the preprocessor search path, unify by expliciting the tcg/ directory. Patch created mechanically by running: $ for x in \ tcg.h tcg-mo.h tcg-op.h tcg-opc.h \ tcg-op-gvec.h tcg-gvec-desc.h; do \ sed -i "s,#include \"$x\",#include \"tcg/$x\"," \ $(git grep -l "#include \"$x\""); \ done Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts) Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200101112303.20724-2-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sh4: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
| | | | | | | | | | | | | | There is a small wrinkle with the gUSA instruction. The translator effectively treats a (known) gUSA sequence as a single instruction. For the purposes of the plugin we end up with a long multi-instruction qemu_plugin_insn. If the known sequence isn't detected we shall never run this translation anyway. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* target/sh4: Fix LGPL information in the file headersThomas Huth2019-05-081-1/+1
| | | | | | | | | It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Message-Id: <1550073530-4138-1-git-send-email-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
| | | | | | | | | | In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-13/+14
| | | | | | | | | | | | | | | | | | | | CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
* sh4: fix use_icount with linux-userLaurent Vivier2018-08-201-0/+1
| | | | | | | | | | | | | | | | | | | | | This fixes java in a linux-user chroot: $ java --version qemu-sh4: .../accel/tcg/cpu-exec.c:634: cpu_loop_exec_tb: Assertion `use_icount' failed. qemu: uncaught target signal 6 (Aborted) - core dumped Aborted (core dumped) In gen_conditional_jump() in the GUSA_EXCLUSIVE part, we must reset base.is_jmp to DISAS_NEXT after the gen_goto_tb() as it is done in gen_delayed_conditional_jump() after the gen_jump(). Bug: https://bugs.launchpad.net/qemu/+bug/1768246 Fixes: 4834871bc95b67343248100e2a75ae0d287bc08b ("target/sh4: Convert to DisasJumpType") Reported-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20180811082328.11268-1-laurent@vivier.eu>
* target/sh4: Fix translator.c assertion failure for gUSARichard Henderson2018-07-091-37/+44
| | | | | | | | | | | | The translator loop does not allow the tb_start hook to set dc->base.is_jmp; the only hook allowed to do that is translate_insn. Split the work between init_disas_context where we validate the gUSA parameters, and translate_insn where we emit code. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-4/+4
| | | | | | | | | Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sh4: convert to TranslatorOpsEmilio G. Cota2018-05-091-85/+86
| | | | | | | | | | | This was fairly straightforward since it had already been converted to DisasContextBase; just had to add TARGET_TOO_MANY to the switch in tb_stop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson2017-12-291-2/+2
| | | | | | | These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sh4: Convert to DisasContextBaseRichard Henderson2017-12-181-76/+78
| | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> [aurel32: fix whitespace] Message-Id: <20170907185057.23421-5-richard.henderson@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Do not singlestep after exceptionsRichard Henderson2017-12-181-16/+16
| | | | | | | | | | If we've already raised an exception (and set NORETURN), do not emit unreachable code to raise a debug exception. Note that gen_goto_tb takes single-stepping into account. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170907185057.23421-4-richard.henderson@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Convert to DisasJumpTypeRichard Henderson2017-12-181-35/+30Star
| | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170907185057.23421-3-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson2017-12-181-22/+60
| | | | | | | | | | | As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170907185057.23421-2-richard.henderson@linaro.org> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: fix TCG leak during gusa sequenceAlex Bennée2017-12-181-1/+1
| | | | | | | | | | | | | | | This fixes bug #1735384 while running java under qemu-sh4. When debug was enabled it showed a problem with TCG temps. Once fixed I was able to run java -version normally. Cc: qemu-stable@nongnu.org Reported-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20171206093050.25308-1-alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: add missing tcg_temp_free() in _decode_opc()Philippe Mathieu-Daudé2017-12-181-0/+2
| | | | | | | | | missed in c55497ecb8c and 852d481faf7. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20171205170013.22337-3-f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Remove empty statementsLadi Prosek2017-12-181-1/+1
| | | | | | | | | | | | | Thanks to Laszlo Ersek for spotting the double semicolon in target/i386/kvm.c I have trivially grepped the tree for ';;' in C files. Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/sh4: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-1/+1
| | | | | | | | | | | | | | | | | | Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-7/+0Star
|/ | | | | | | | | | Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Acked-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota2017-10-101-2/+2
| | | | | | | | | | | | It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
| | | | | | | | | | | | | Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson2017-07-181-10/+20
| | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-28-rth@twiddle.net> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Implement fsrraRichard Henderson2017-07-181-0/+2
| | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-27-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson2017-07-181-0/+2
| | | | | | | | | Both frchg and fschg require PR == 0, otherwise undefined_operation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-26-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Implement fpchgRichard Henderson2017-07-181-0/+5
| | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-25-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Introduce CHECK_SH4ARichard Henderson2017-07-181-34/+30Star
| | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-24-rth@twiddle.net> [aurel32: fix conflict] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson2017-07-181-26/+31
| | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-23-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Tidy misc illegal insn checksRichard Henderson2017-07-181-9/+13
| | | | | | | | | | | | Now that we have a do_illegal label, use goto in order to self-document the forcing of the exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-22-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson2017-07-181-10/+14
| | | | | | | | | | We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-21-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson2017-07-181-10/+4Star
| | | | | | | | | | We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-20-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson2017-07-181-6/+5Star
| | | | | | | | | | We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-19-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson2017-07-181-4/+4
| | | | | | | | | | We do not need to form full 64-bit quantities in order to perform the move. This reduces code expansion on 64-bit hosts. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-18-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson2017-07-181-39/+36Star
| | | | | | | | | | | This enforces proper alignment and makes the register update more natural. Note that there is a more serious bug fix for fmov {DX}Rn,@(R0,Rn) to use a store instead of a load. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-17-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Merge DREG into fpr64 routinesRichard Henderson2017-07-181-11/+15
| | | | | | | | | | | Also add a debugging assert that we did signal illegal opc for odd double-precision registers. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-16-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Eliminate unused XREG macroRichard Henderson2017-07-181-1/+0Star
| | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-15-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Hoist fp register bank selectionRichard Henderson2017-07-181-3/+5
| | | | | | | | | Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-14-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson2017-07-181-13/+13
| | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-13-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Unify cpu_fregs into FREGRichard Henderson2017-07-181-73/+52Star
| | | | | | | | | | | | | We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-12-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Hoist register bank selectionRichard Henderson2017-07-181-10/+11
| | | | | | | | | Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-11-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Recognize common gUSA sequencesRichard Henderson2017-07-181-0/+321
| | | | | | | | | | | For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-8-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Handle user-space atomicsRichard Henderson2017-07-181-12/+126
| | | | | | | | | | | | | | | | | For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. For QEMU, we cannot do this in quite the same way. Instead, we notice the normal start of such a sequence (mov #-x,r15), and start a new TB that can be executed under cpu_exec_step_atomic. Reported-by: Bruno Haible <bruno@clisp.org> LP: https://bugs.launchpad.net/bugs/1701971 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-7-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson2017-07-181-2/+2
| | | | | | | | | | | We'll be putting more things into this bitmask soon. Let's have a name that covers all possible uses. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-4-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: Consolidate end-of-TB testsRichard Henderson2017-07-181-14/+17
| | | | | | | | | | We can fold 3 different tests within the decode loop into a more accurate computation of max_insns to start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-3-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: return result of fcmp using TCGAurelien Jarno2017-07-181-4/+6
| | | | | | | | | | Since that the T bit of the SR register is mapped using a TGC global, it's better to return the value through TCG than writing it directly. It allows to declare the helpers with the flag TCG_CALL_NO_WG. Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target/sh4: do not use a helper to implement fnegAurelien Jarno2017-07-181-3/+2Star
| | | | | | | | | There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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