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path: root/target/sh4/translate.c
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* target/sh4: fix some comment spelling errorsLichang Zhao2020-10-271-1/+1
* target/sh4: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2020-10-271-3/+5
* target/sh4: Remove superfluous breaksLiao Pingfang2020-09-011-3/+0Star
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/sh4: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
* target/sh4: Fix LGPL information in the file headersThomas Huth2019-05-081-1/+1
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-13/+14
* sh4: fix use_icount with linux-userLaurent Vivier2018-08-201-0/+1
* target/sh4: Fix translator.c assertion failure for gUSARichard Henderson2018-07-091-37/+44
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-4/+4
* target/sh4: convert to TranslatorOpsEmilio G. Cota2018-05-091-85/+86
* tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson2017-12-291-2/+2
* target/sh4: Convert to DisasContextBaseRichard Henderson2017-12-181-76/+78
* target/sh4: Do not singlestep after exceptionsRichard Henderson2017-12-181-16/+16
* target/sh4: Convert to DisasJumpTypeRichard Henderson2017-12-181-35/+30Star
* target/sh4: Use cmpxchg for movco when parallel_cpusRichard Henderson2017-12-181-22/+60
* target/sh4: fix TCG leak during gusa sequenceAlex Bennée2017-12-181-1/+1
* target/sh4: add missing tcg_temp_free() in _decode_opc()Philippe Mathieu-Daudé2017-12-181-0/+2
* Remove empty statementsLadi Prosek2017-12-181-1/+1
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-4/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | target/sh4: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-1/+1
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
* | qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-7/+0Star
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* tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota2017-10-101-2/+2
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson2017-07-181-10/+20
* target/sh4: Implement fsrraRichard Henderson2017-07-181-0/+2
* target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson2017-07-181-0/+2
* target/sh4: Implement fpchgRichard Henderson2017-07-181-0/+5
* target/sh4: Introduce CHECK_SH4ARichard Henderson2017-07-181-34/+30Star
* target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson2017-07-181-26/+31
* target/sh4: Tidy misc illegal insn checksRichard Henderson2017-07-181-9/+13
* target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson2017-07-181-10/+14
* target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson2017-07-181-10/+4Star
* target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson2017-07-181-6/+5Star
* target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson2017-07-181-4/+4
* target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson2017-07-181-39/+36Star
* target/sh4: Merge DREG into fpr64 routinesRichard Henderson2017-07-181-11/+15
* target/sh4: Eliminate unused XREG macroRichard Henderson2017-07-181-1/+0Star
* target/sh4: Hoist fp register bank selectionRichard Henderson2017-07-181-3/+5
* target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson2017-07-181-13/+13
* target/sh4: Unify cpu_fregs into FREGRichard Henderson2017-07-181-73/+52Star
* target/sh4: Hoist register bank selectionRichard Henderson2017-07-181-10/+11
* target/sh4: Recognize common gUSA sequencesRichard Henderson2017-07-181-0/+321
* target/sh4: Handle user-space atomicsRichard Henderson2017-07-181-12/+126
* target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson2017-07-181-2/+2
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