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* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-3/+2Star
* target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson2017-07-181-10/+20
* target/sh4: Implement fsrraRichard Henderson2017-07-183-0/+19
* target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson2017-07-181-0/+2
* target/sh4: Implement fpchgRichard Henderson2017-07-181-0/+5
* target/sh4: Introduce CHECK_SH4ARichard Henderson2017-07-181-34/+30Star
* target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson2017-07-181-26/+31
* target/sh4: Tidy misc illegal insn checksRichard Henderson2017-07-181-9/+13
* target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson2017-07-181-10/+14
* target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson2017-07-181-10/+4Star
* target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson2017-07-181-6/+5Star
* target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson2017-07-181-4/+4
* target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson2017-07-181-39/+36Star
* target/sh4: Merge DREG into fpr64 routinesRichard Henderson2017-07-181-11/+15
* target/sh4: Eliminate unused XREG macroRichard Henderson2017-07-181-1/+0Star
* target/sh4: Hoist fp register bank selectionRichard Henderson2017-07-181-3/+5
* target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson2017-07-181-13/+13
* target/sh4: Unify cpu_fregs into FREGRichard Henderson2017-07-181-73/+52Star
* target/sh4: Hoist register bank selectionRichard Henderson2017-07-181-10/+11
* target/sh4: Recognize common gUSA sequencesRichard Henderson2017-07-181-0/+321
* target/sh4: Handle user-space atomicsRichard Henderson2017-07-184-15/+148
* target/sh4: Adjust TB_FLAG_PENDING_MOVCARichard Henderson2017-07-181-3/+3
* target/sh4: Keep env->flags cleanRichard Henderson2017-07-182-2/+2
* target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson2017-07-182-3/+5
* target/sh4: Consolidate end-of-TB testsRichard Henderson2017-07-181-14/+17
* target/sh4: return result of fcmp using TCGAurelien Jarno2017-07-183-16/+18
* target/sh4: do not use a helper to implement fnegAurelien Jarno2017-07-183-9/+2Star
* target/sh4: fix FPSCR cause vs flag inversionAurelien Jarno2017-07-181-10/+10
* target/sh4: fix FPU unorderered compareAurelien Jarno2017-07-181-20/+8Star
* target/sh4: do not check for PR bit for fabs instructionAurelien Jarno2017-07-183-24/+3Star
* target/sh4: fix RTE instruction delay slotAurelien Jarno2017-05-302-5/+16
* target/sh4: ignore interrupts in a delay slotAurelien Jarno2017-05-301-2/+10
* target/sh4: introduce DELAY_SLOT_MASKAurelien Jarno2017-05-303-12/+12
* target/sh4: fix reset when using a kernel and an initrdAurelien Jarno2017-05-301-1/+9
* target/sh4: log unauthorized accesses using qemu_log_maskAurelien Jarno2017-05-301-1/+1
* target/sh4: use cpu_loop_exit_restoreAurelien Jarno2017-05-131-8/+2Star
* target/sh4: trap unaligned accessesAurelien Jarno2017-05-134-2/+25
* target/sh4: movua.l is an SH4-A only instructionAurelien Jarno2017-05-131-11/+15
* target/sh4: implement tas.b using atomic helperAurelien Jarno2017-05-131-12/+7Star
* target/sh4: generate fences for SH4Aurelien Jarno2017-05-131-4/+5
* target/sh4: optimize gen_write_sr using extract opAurelien Jarno2017-05-131-6/+3Star
* target/sh4: optimize gen_store_fpr64Aurelien Jarno2017-05-131-7/+1Star
* target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jumpAurelien Jarno2017-05-131-6/+3Star
* target/sh4: only save flags state at the end of the TBAurelien Jarno2017-05-131-36/+33Star
* target/sh4: fix BS_EXCP exitAurelien Jarno2017-05-131-9/+7Star
* target/sh4: fix BS_STOP exitAurelien Jarno2017-05-131-2/+3
* target/sh4: move DELAY_SLOT_TRUE flag into a separate globalAurelien Jarno2017-05-133-18/+16Star
* target/sh4: do not include DELAY_SLOT_TRUE in the TB stateAurelien Jarno2017-05-131-2/+1Star
* target/sh4: get rid of DELAY_SLOT_CLEARMEAurelien Jarno2017-05-133-16/+6Star
* target/sh4: split ctx->flags into ctx->tbflags and ctx->envflagsAurelien Jarno2017-05-131-79/+82
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