summaryrefslogtreecommitdiffstats
path: root/target/sparc/cpu.h
Commit message (Expand)AuthorAgeFilesLines
* sparc: cleanup cpu type name compositionIgor Mammedov2017-10-271-0/+3
* qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-1/+1
* sparc: Fix typedef clashDr. David Alan Gilbert2017-09-141-2/+2
* sparc: replace cpu_sparc_init() with cpu_generic_init()Igor Mammedov2017-09-011-2/+1Star
* sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov2017-09-011-4/+4
* target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2017-01-181-0/+3
* target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2017-01-181-0/+2
* target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-181-30/+18Star
* target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2017-01-181-4/+3Star
* target-sparc: implement UA2005 GL registerArtyom Tarasenko2017-01-181-0/+2
* target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko2017-01-181-0/+1
* target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2017-01-181-2/+2
* target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko2017-01-181-0/+1
* target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko2017-01-181-1/+2
* target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko2017-01-181-0/+4
* target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko2017-01-181-0/+17
* target-sparc: use explicit mmu register pointersArtyom Tarasenko2017-01-181-0/+4
* target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko2017-01-181-0/+17
* target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2017-01-181-0/+2
* qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-131-0/+3
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+779
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-03 15:53:08 +0100