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* shutdown: Add source information to SHUTDOWN and RESETEric Blake2017-05-231-1/+1
* sparc/sparc64: grab BQL before calling cpu_check_irqsAlex Bennée2017-03-092-0/+16
* target/sparc: Restore ldstub of odd asisRichard Henderson2017-03-011-2/+25
* cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée2017-02-241-3/+5
* monitor: Fix crashes when using HMP commands without CPUThomas Huth2017-02-211-0/+4
* migration: extend VMStateInfoJianjun Duan2017-01-241-2/+4
* target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko2017-01-181-0/+11
* target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2017-01-182-8/+47
* target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko2017-01-181-0/+31
* target-sparc: add more registers to dump_mmuArtyom Tarasenko2017-01-181-0/+2
* target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko2017-01-181-0/+22
* target-sparc: allow 256M sized pagesArtyom Tarasenko2017-01-181-17/+1Star
* target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko2017-01-181-36/+15Star
* target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2017-01-182-22/+104
* target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-183-36/+24Star
* target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko2017-01-181-2/+4
* target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko2017-01-181-0/+1
* target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko2017-01-181-14/+18
* target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2017-01-182-5/+4Star
* target-sparc: fix immediate UA2005 trapsArtyom Tarasenko2017-01-181-1/+1
* target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko2017-01-181-2/+5
* target-sparc: implement UA2005 GL registerArtyom Tarasenko2017-01-186-7/+58
* target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko2017-01-183-5/+39
* target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2017-01-182-3/+7
* target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko2017-01-181-0/+11
* target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko2017-01-183-0/+26
* target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko2017-01-181-3/+2Star
* target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko2017-01-181-1/+2
* target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko2017-01-181-0/+4
* target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko2017-01-181-0/+17
* target-sparc: use explicit mmu register pointersArtyom Tarasenko2017-01-182-12/+58
* target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko2017-01-182-5/+36
* target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2017-01-182-2/+15
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-6/+6
* qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-132-2/+4
* target-sparc: Use ctpop helperRichard Henderson2017-01-103-7/+1Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-2021-0/+13805
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