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path: root/target/xtensa/cpu.h
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* target/xtensa: add DFPU registers and opcodesMax Filippov2020-08-211-0/+3
* target/xtensa: add DFPU optionMax Filippov2020-08-211-0/+2
* target/xtensa: support copying registers up to 64 bits wideMax Filippov2020-08-211-0/+1
* target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov2020-08-211-1/+1
* target/xtensa: implement NMI supportMax Filippov2020-08-211-0/+1
* target/xtensa: make opcode properties more dynamicMax Filippov2020-08-211-4/+1Star
* target/xtensa: fetch HW version from configuration overlayMax Filippov2020-05-171-0/+1
* target/xtensa: statically allocate xtensa_insnbufs in DisasContextMax Filippov2020-04-081-0/+3
* gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
* target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIXRichard Henderson2020-01-161-4/+0Star
* target/xtensa: fix ps.ring use in MPU configsMax Filippov2020-01-061-3/+7
* target/xtensa: linux-user: add call0 ABI supportMax Filippov2019-09-111-0/+3
* configure: Define target access alignment in configuretony.nguyen@bt.com2019-08-201-2/+0Star
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+1
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-2/+0Star
* target/xtensa: Use env_cpu, env_archcpuRichard Henderson2019-06-101-11/+6Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-16/+5Star
* Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell2019-05-211-23/+35
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| * target/xtensa: implement exclusive access optionMax Filippov2019-05-151-0/+2
| * target/xtensa: update list of exception causesMax Filippov2019-05-151-4/+5
| * target/xtensa: implement DIWBUI.P opcodeMax Filippov2019-05-141-0/+1
| * target/xtensa: implement MPU optionMax Filippov2019-05-111-0/+17
| * target/xtensa: add parity/ECC option SRsMax Filippov2019-05-111-0/+6
| * target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov2019-05-111-0/+3
| * target/xtensa: make internal MMU functions staticMax Filippov2019-05-111-19/+0Star
| * target/xtensa: get rid of centralized SR propertiesMax Filippov2019-05-111-0/+1
* | target/xtensa: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
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* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1Star
* target: Clean up how the dump_mmu() printMarkus Armbruster2019-04-181-1/+1
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
* target/xtensa: implement PREFCTL SRMax Filippov2019-02-281-0/+1
* target/xtensa: prioritize load/store in FLIX bundlesMax Filippov2019-02-281-0/+4
* target/xtensa: reorganize register handling in translatorsMax Filippov2019-02-281-3/+12
* target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov2019-02-281-0/+1
* target/xtensa: add generic instruction post-processingMax Filippov2019-02-281-0/+8
* target/xtensa: sort FLIX instruction opcodesMax Filippov2019-02-281-0/+2
* target/xtensa: allow multiple names for single opcodeMax Filippov2019-02-191-1/+3
* target/xtensa: don't require opcode table sortingMax Filippov2019-02-191-2/+0Star
* target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov2019-02-191-1/+0Star
* target/xtensa: don't specify windowed registers manuallyMax Filippov2019-02-111-1/+1
* target/xtensa: expose core runstall as an IRQ lineMax Filippov2019-01-281-0/+2
* target/xtensa: rearrange access to external interruptsMax Filippov2019-01-281-2/+3
* target/xtensa: drop function xtensa_timer_irqMax Filippov2019-01-281-1/+0Star
* target/xtensa: rework zero overhead loops implementationMax Filippov2019-01-121-0/+32
* target/xtensa: extract test for cpdisabled exceptionMax Filippov2018-10-011-0/+1
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