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* target/xtensa: use MPU background map from core configurationMax Filippov2020-01-061-1/+14
| | | | | | | | Configuration overlay may define MPU background map. Import core-matmap.h from the overlay and use XCHAL_MPU_BACKGROUND_MAP macro if it's defined. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement exclusive access optionMax Filippov2019-05-151-2/+6
| | | | | | | | | | | The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement DIWBUI.P opcodeMax Filippov2019-05-141-0/+1
| | | | | | This is a recent addition to the set of data cache opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement MPU optionMax Filippov2019-05-111-0/+29
| | | | | | | | | | | | | The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region Protection Option or the Region Translation Option but without any translation capability. It does no demand paging and does not reference a memory-based page table. Add memory protection unit option, internal state, SRs and opcodes. Implement MPU entries dumping in dump_mmu. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: add parity/ECC option SRsMax Filippov2019-05-111-0/+2
| | | | | | | Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option. The implementation is trivial since we don't emulate parity/ECC yet. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov2019-05-111-0/+3
| | | | | | | IDMA and scatter/gather features introduced new IRQ types that overlay_tool.h need to initialize Xtensa configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov2019-02-191-1/+0Star
| | | | | | | Don't run xtensa_finalize_config at the time of core registration, instead run it at the CPU class initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: rework zero overhead loops implementationMax Filippov2019-01-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | Don't invalidate TB with the end of zero overhead loop when LBEG or LEND change. Instead encode the distance from the start of the page where the TB starts to the LEND in the TB cs_base and generate loopback code when the next PC matches encoded LEND. Distance to a destination within the same page and up to a maximum instruction length into the next page is encoded literally, otherwise it's zero. The distance from LEND to LBEG is also encoded in the cs_base: it's encoded literally when less than 256 or as 0 otherwise. This allows for TB chaining for the loopback branch at the end of a loop for the most common loop sizes. With this change the resulting emulation speed is about 10% higher in softmmu mode on uClibc-ng and LTP tests. Emulation speed in linux user mode is a few percent lower because there's no direct TB chaining between different memory pages. Testing with lower limit on direct TB chaining range shows gradual slowdown to ~15% for the block size of 64 bytes and ~50% for the block size of 32 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/xtensa: check zero overhead loop alignmentMax Filippov2018-06-301-0/+1
| | | | | | | | | ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: use correct number of registers in gdbstubMax Filippov2018-03-131-3/+8
| | | | | | | | | | System emulation should provide access to all registers, userspace emulation should only provide access to unprivileged registers. Record register flags from GDB register map definition, calculate both num_regs and num_core_regs if either is zero. Use num_regs in system emulation, num_core_regs in userspace emulation gdbstub. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: fix default sysrom/sysram addressesMax Filippov2018-01-111-4/+4
| | | | | | noMMU configs had wrong sysrom and sysram base addresses, fix them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: sim: instantiate local memoriesMax Filippov2017-02-231-0/+160
| | | | | | | | Xtensa core may have a number of RAM and ROM areas configured. Record their size and location from the core configuration overlay and instantiate them as RAM regions in the SIM machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target-xtensa: implement RER/WER instructionsMax Filippov2017-01-171-1/+6
| | | | | | | | | RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: implement MEMCTL SRMax Filippov2017-01-151-0/+15
| | | | | | | MEMCTL SR controls zero overhead loop buffer and number of ways enabled in L1 caches. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov2017-01-151-2/+2
| | | | | | | | | | Configuration overlay does not explicitly say whether there are ICACHE and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect if corresponding cache option is enabled, but that's not correct: on cores without cache these macros are defined as 1, not as 0. Check XCHAL_[ID]CACHE_SIZE instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: add static vectors selectionMax Filippov2017-01-151-1/+10
| | | | | | | Xtensa cores may have two distinct addresses for the static vectors group. Provide a function to select one of them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+602
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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